G06F11/3636

Systems for exchange of data between remote devices

Application debug protocols that require waiting for responses between each request may be adversely affected if significant latency exists between a test device executing an application and a remote device used to debug the application. To address this, the test device is connected to a separate device that receives requests from the remote device. When a first request is received, the separate device determines other requests that are related to the first request, sequentially sends the other requests to the test device, and receives a response after each request, using a wired connection affected by less latency than communication with the remote device. The separate device then sends each of the requests and responses to the remote device for storage. When the remote device prepares to send a subsequent request, if a response can be determined using the stored data, the stored data is used to determine the response locally.

ANALYSIS FUNCTION IMPARTING DEVICE, ANALYSIS FUNCTION IMPARTING METHOD, AND ANALYSIS FUNCTION IMPARTING PROGRAM

An analysis function imparting device (10) includes a virtual machine analyzing unit (121) that analyzes a virtual machine of a script engine, a command set architecture analyzing unit (122) that analyzes a command set architecture that is a command system of the virtual machine, and an analysis function imparting unit (123) that performs hooking for imparting multipath execution functions to the script engine, on the basis of architecture information acquired by the analysis performed by the virtual machine analyzing unit (121) and the command set architecture analyzing unit (122).

Microchip with on-chip debug and trace engine
20230229583 · 2023-07-20 ·

A microchip includes a central processing unit (CPU) configured to execute a software application. The microchip further includes an Ethernet interface configured to transmit Ethernet packets to and receive Ethernet packets from an external debugging entity. The microchip further includes an on-chip debug and trace module configured to transform debugging data and trace data from the CPU into a stream of Ethernet packets, and to provide the stream of Ethernet packets to the Ethernet interface for transmitting the stream of Ethernet packets to the external debugging entity.

FULLY TRACEABLE AND INTERMEDIATELY DETERMINISTIC RULE CONFIGURATION AND ASSESSMENT FRAMEWORK
20230024024 · 2023-01-26 ·

A method includes assessing an input in a buffer against a rule in a first node of a rule tree to determine that an action should be performed and updating the buffer with results of performing the action. The method also includes inserting an indication of the input, the rule, and the results of performing the action into a tracker log and passing the updated buffer to a second node in the rule tree in response to determining that the first node points to the second node.

Apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry

An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.

INFORMATION PROCESSING APPARATUS, PROCESSING METHOD FOR INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM
20230229582 · 2023-07-20 ·

An information processing apparatus includes a code execution unit that executes a source code and a resource opening unit that opens resources included in an open resource list in a case where there is no difference between resources used for executing the source code and the open resource list.

Machine learning-based techniques for providing focus to problematic compute resources represented via a dependency graph

Methods, systems, apparatuses, and computer-readable storage mediums are described for machine learning-based techniques for reducing the visual complexity of a dependency graph that is representative of an application or service. For example, the dependency graph is generated that comprises a plurality of nodes and edges. Each node represents a compute resource (e.g., a microservice) of the application or service. Each edge represents a dependency between nodes coupled thereto. A machine learning-based classification model analyzes each of the nodes to determine a likelihood that each of the nodes is a problematic compute resource. For instance, the classification model may output a score indicative of the likelihood that a particular compute resource is problematic. The nodes and/or edges having a score that exceed a predetermined threshold are provided focus via the dependency graph.

Data model generation using generative adversarial networks

Methods for generating data models using a generative adversarial network can begin by receiving a data model generation request by a model optimizer from an interface. The model optimizer can provision computing resources with a data model. As a further step, a synthetic dataset for training the data model can be generated using a generative network of a generative adversarial network, the generative network trained to generate output data differing at least a predetermined amount from a reference dataset according to a similarity metric. The computing resources can train the data model using the synthetic dataset. The model optimizer can evaluate performance criteria of the data model and, based on the evaluation of the performance criteria of the data model, store the data model and metadata of the data model in a model storage. The data model can then be used to process production data.

Efficient fuzz testing of low-level virtual devices
11556458 · 2023-01-17 · ·

Examples described herein include systems and methods for fuzz testing low-level virtual devices and virtual devices with DMA write functionality. A fuzz tester includes components distributed across a virtual machine and its host system. The fuzz testing components in the virtual machine are implemented as firmware installed in the virtual machine's ROM. These components operate independent of data stored in the virtual machine's RAM and do not require an operating system to be installed on the virtual machine. As a result, any changes made to the virtual machine's RAM during the fuzzing process by low-level virtual devices or virtual devices with DMA write functionality cannot interrupt the fuzz testing or otherwise negatively impact the fuzz tester itself.

Malware detection in memory

A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (202). The processor can also detect an invalid indirect branch instruction from the processor trace information (204) and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (206). Additionally, the processor can block the application from accessing or modifying memory (208).