The disclosure describes techniques that enable detection of memory leaks of software executing on devices within a computer network. An example network device includes memory and processing circuitry. The processing circuitry monitors a usage of the memory by a software component operating within the network device. The processing circuitry periodically determines a memory growth pattern score for the software component based on the usage of the memory. The processing circuitry also predicts whether the user-level process is experiencing a memory leak based on the memory growth pattern score. The processing circuitry applies confirmation criteria to current memory usage of the software component to confirm that the software component is experiencing the memory leak. When the software component is experiencing the memory leak, the processing circuitry generates an alert.

The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

This disclosure concerns tools and techniques for debugging a quantum program (e.g., a program used to configure and control a quantum computing device). Because the state space of a quantum program is so much larger and less structured than the state space for a classical program, new techniques are required to help the program developer and coder determine whether or not their program is working correctly and to identify errors if not. The disclosed technology provides tools and techniques for debugging quantum programs using a classical computer.

An electronic computing system preserves a pre-error state of a processing unit by receiving a first stream of inputs; buffering the first stream of inputs to generate a buffered stream of inputs identical to the first stream of inputs; conveying the first stream to a primary instance of a first program; conveying the buffered stream to a secondary instance of the first program; executing the primary instance on the first stream in real time; executing the secondary instance on the buffered stream with a predefined time delay with respect to execution of the primary instance on the first stream; detecting an error state resulting from execution of the primary instance; and in response to detecting the error state, pausing the secondary instance and preserving a current state of the secondary instance, wherein the current state of the secondary instance corresponds to a pre-error state of the primary instance.

An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

A system coordinates with remote hardware to execute customer workloads. The system uses an architecture for ensuring trust to ensure that debugging is not performed at the remote hardware while the customer workload is being executed on the remote hardware without customer consent. For example, debugging at the remote hardware may enable an entity performing the debugging to view certain aspects of the customer's workload. The architecture for ensuring trusts uses a shared secret to ensure customer consent is given before debugging can be performed while the customer's workload is being executed on the remote hardware.

A method may include receiving, at a storage device, a command using a storage protocol, wherein the storage device is configured to execute a user program, and executing, at the storage device, a device program based on the command. The command may be a first command, and the method may further include receiving, at the storage device, using the storage protocol, a second command, and sending, from the storage device, using the storage protocol, information about the device program based on the second command. The method may further include sending, from the storage device, using the storage protocol, a list of device programs supported by the storage device based on the second command. The method may further include providing, by the storage device, output data from the device program. The providing may include sending, from the storage device, using the storage protocol, a log message.

A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.