Patent classifications
G06F12/023
Markers for hash code calculations on occupied portions of data blocks
A method for performing hash code calculations may include calculating, during a write operation for a data block, a hash code for an occupied portion of the data block, inserting, during the write operation, a marker into the data block, calculating, during a read operation for the data block, a hash code for the occupied portion of the data block, searching, during the read operation, for the marker in the data block, and terminating the hash code calculation in response to finding the marker. A system may include a first interface configured to receive data blocks, a second interface configured to transmit data blocks, and hash logic coupled between the first and second interfaces, wherein the hash logic is configured to calculate a hash code for the occupied portion of a data block received through the first interface, and insert a marker in an unoccupied portion of the data block.
COMPRESSED DATA MANAGEMENT IN ZONES
Systems, methods, and computer readable storage mediums for optimistically managing compressed data in a storage system. When possible, multiple input blocks are compressed into a buffer and stored in a single physical block on a storage device. The metadata of the multiple input blocks can be managed separately. A fingerprint of the compressed buffer can be generated and used as an index to the single physical block. Alternatively, fingerprints of the uncompressed input blocks can be generated, and reference counts can be maintained to track the number of input blocks which reference the compressed buffer. In some embodiments the physical block is associated with a zone represented by a virtual construct, wherein the zone is dynamically mapped to underlying storage of the zoned storage system.
System and method for managing storage space
Disclosed herein is a technique for managing storage space in a user device. Users are provided with options to manage storage space usage in an organized and efficient manner. The options can include recommendations to the user regarding automatically and/or manually purging data from the user device to free up a particular amount of storage space that is needed to carry out a particular task.
Saving virtual memory space in a clone environment
Virtual memory space may be saved in a clone environment by leveraging the similarity of the data signatures in swap files when a chain of virtual machines (VMs) includes clones spawned from a common parent and executing common applications. Deduplication is performed across the chain, rather than merely within each VM. Examples include generating a common deduplication identifier (ID) for the chain; generating a logical addressing table linked to the deduplication ID, for each of the VMs in the chain; and generating a hash table for the chain. Examples further include, based at least on a swap out request, generating a hash value for a block of memory to be written to a storage medium; and based at least on finding the hash value within the hash table, updating the logical addressing table to indicate a location of a prior-existing duplicate of the block on the storage medium.
Providing multiple memory modes for a processor including internal memory
In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
Parallel processing device
There is provided a parallel processing device which allows consecutive parallel data processing to be performed. The parallel processing device includes: a plurality of addition units configured to selectively receive input data among output data from the plurality of input units according to configuration values for each addition unit of the plurality of addition units, and perform addition operation for the input data in parallel; and the plurality of the delay units configured to delay input data for one cycle. Each delay unit of the plurality of the delay units delays output data from each addition unit of the plurality of addition units and outputs the delayed output data to each input unit of the plurality of input units.
SYSTEMS, METHODS, AND APPARATUS FOR WEAR-LEVEL AWARE MEMORY ALLOCATION
A method for memory allocation may include determining an amount of use for a first memory page, wherein the first memory page is mapped to a first page group of a first group level, a second memory page may be mapped to a second page group of the first group level, and the first memory page and the second memory page may be mapped to a third page group of a second group level, and selecting, based on an allocation request, the first memory page based on the amount of use. The amount of use may include a first amount of use, and the method may further include determining a second amount of use for the second memory page, wherein the first memory page may be selected based on the first amount of use and the second amount of use.
Thread associated memory allocation and memory architecture aware allocation
A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.
Determination of memory access patterns of tasks in a multi-core processor
A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.
BUFFER POOL MANAGEMENT
A processor may allocate a first buffer segment from a buffer pool. The first buffer segment may be configured with a first contiguous range of memory for a first data partition of a data table. The first data partition comprising a first plurality of data blocks. A processor may store the first plurality of data blocks in order into the first buffer segment. A processor may retrieve the target data block from the first buffer segment in response to a data access request for a target data block of the first plurality of data blocks.