G06F12/023

METHOD AND APPARATUS FOR REDUCING OPERATION OF GARBAGE COLLECTION
20230033562 · 2023-02-02 ·

A method, performed by an electronic device, includes: based on a target event associated with an application being initiated, transmitting initiation of the target event to a runtime environment of the application, and after transmitting the initiation of the target event to the runtime environment, based on a memory value allocated to the application exceeding a threshold value for determining whether to initiate a garbage collection, skipping performing the garbage collection and updating a bound memory value, defined in the garbage collection, and the threshold value.

CONSISTENT HASHING FOR COMMUNICATION DEVICES

A method for allocating a device-specific resource from one or more databases is provided. The method includes receiving, at an interface, a coupling identifier including a pool identifier and a resource identifier, as part of a processing request from a requesting entity, the processing request including a request for the device-specific resource, wherein the coupling identifier associates the requesting entity with the device-specific resource based on the resource identifier, extracting, at the interface, the pool identifier from the coupling identifier, identifying, by the interface, the processing service in which the device-specific resource associated with the resource identifier is cached, based on the pool identifier, and transmitting, from the interface to the identified processing service, at least a part of the processing request to process the cached requested device-specific resource.

Memory system with hierarchical tables

A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

APPLICATION PROGRAMMING INTERFACE TO INDICATE MEMORY INFORMATION
20220342710 · 2022-10-27 ·

Apparatuses, systems, and techniques to execute one or more application programming interface (API) functions to facilitate parallel computing. In at least one embodiment, one or more APIs are to indicate information about one or more storage locations using various novel techniques described herein.

Booting an application from multiple memories

A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Calculation method and related product

The present disclosure provides a computing method that is applied to a computing device. The computing device includes: a memory, a register unit, and a matrix computing unit. The method includes the following steps: controlling, by the computing device, the matrix computing unit to obtain a first operation instruction, where the first operation instruction includes a matrix reading instruction for a matrix required for executing the instruction; controlling, by the computing device, an operating unit to send a reading command to the memory according to the matrix reading instruction; and controlling, by the computing device, the operating unit to read a matrix corresponding to the matrix reading instruction in a batch reading manner, and executing the first operation instruction on the matrix. The technical solutions in the present disclosure have the advantages of fast computing speed and high efficiency.

Method of managing integrated circuits cards by widening the biggest empty region, corresponding card and apparatus
11481133 · 2022-10-25 · ·

A method of managing an integrated circuit memory includes having an integrated circuit card with a memory space including memory space regions for storing user profile data. The memory space is partitioned into segments of memory space regions, where the segments of memory space regions includes allocated regions and empty regions. From the empty regions, the biggest empty region of the memory space is selected. The selected biggest empty region is widened by moving memory blocks positioned in a subset of allocated regions that are at boundaries of the selected biggest empty region into other available empty regions.

SAVING VIRTUAL MEMORY SPACE IN A CLONE ENVIRONMENT
20230080935 · 2023-03-16 ·

Virtual memory space may be saved in a clone environment by leveraging the similarity of the data signatures in swap files when a chain of virtual machines (VMs) includes clones spawned from a common parent and executing common applications. Deduplication is performed across the chain, rather than merely within each VM. Examples include generating a common deduplication identifier (ID) for the chain; generating a logical addressing table linked to the deduplication ID, for each of the VMs in the chain; and generating a hash table for the chain. Examples further include, based at least on a swap out request, generating a hash value for a block of memory to be written to a storage medium; and based at least on finding the hash value within the hash table, updating the logical addressing table to indicate a location of a prior-existing duplicate of the block on the storage medium.

Adaptive caching for hybrid columnar databases with heterogeneous page sizes

Disclosed herein are system, method, and computer program product embodiments for adaptive caching for hybrid columnar databases with heterogeneous page sizes. An embodiment operates by receiving a request to load a new page of memory from a disk in a buffer cache. The embodiment scans one or more pools comprising one or more pages of the same size in a buffer cache. The embodiment determines an increment of a reuse rate for the pools in the buffer cache within a time interval. The embodiment determines a cumulative reuse rate that is the sum of the increments of the reuse rate over several time intervals. The embodiment determines a gliding average reuse rate of the cumulative reuse rate over several time intervals. The embodiment compares the average reuse rates of the plurality of the pools to a threshold to dynamically determine whether a pool should reuse memory from the existing pages of the same pool or rebalance memory from one or more victim pools.

High-speed graph processor for graph searching and simultaneous frontier determination

A computer architecture for graph processing employs a high-bandwidth memory closely coupled to independent processing elements for searching through a graph using a first set of processing elements operating simultaneously to determine neighbors to a current frontier and second processing elements operating simultaneously to determine a next frontier, this process being repeated to search through graph nodes.