The present disclosure provides a memory management method, and belongs to the technical field of networks. The method includes: allocating a first memory address to video frame data based on a memory multiplexing queue, wherein the memory multiplexing queue records a memory address of video frame data that has been rendered; storing the video frame data in a memory space indicated by the first memory address; and adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data.

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

A data storage device includes a memory device and a controller coupled to the memory device. The memory device includes a plurality of super devices. The controller is configured to set a free space threshold value for amount of free space that each super device of the plurality of super devices can have, determine that at least one super device of the plurality of super devices is at or above the free space threshold, determine that cold zones are disposed in more than one super device of the plurality of super devices, move data from the cold zones to a first super device of the plurality of super devices wherein after moving the data, all super devices are below the free space threshold, and allocate all new super blocks among the plurality of super devices without allocating any new super blocks to the first super device.

A balloon memory fragmentation reduction system includes a memory, at least one processor in communication with the memory, a guest operating system (OS) including a device driver, and a hypervisor executing on the at least one processor. The hypervisor is configured to record an amount of memory allocated by the device driver of the guest OS, locate a contiguous region of guest memory addresses according to the amount of memory allocated by the device driver, reserve the contiguous region of guest memory addresses, and notify the guest OS that the contiguous region of guest memory addresses is reserved.

Techniques for deserializing stream objects are disclosed. The system may receive data representing a stream object. The data can include an object descriptor, a class descriptor, and stream field values corresponding to the stream object. The system may select a particular deserialization process, from among a plurality of deserialization processes. The selection may be based at least in part on the object descriptor and the class descriptor. The system can deserialize the data representing the stream object using the selected deserialization process, yielding one or more deserialized objects.

A memory management system includes a physical memory associated with a computing device and a memory manager. The memory manager is configured to manage a shared memory cache as part of a compression of the physical memory using a cache compression algorithm, wherein a compression block size for the compression is a single cache line size. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses a memory descriptor defined by an STT entry having a cache line map and a plurality of sector pointers to load cache from the physical memory to a level 3 Cache. The cache line map contains cache line metadata including a size of each cache line, a location of the cache line in one of the sectors pointed to by the STT entry, and a plurality of flags.

Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.

A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

A convolution operation method includes: configuring an operation apparatus according to a partition rule; reading an operation data partition; reading a depthwise convolution parameter partition to perform a depthwise weighting operation to generate a depthwise weighted partition; performing a depthwise offset operation to generate a depthwise convolution operation result partition; reading a pointwise convolution parameter partition to perform a pointwise weighting operation on the depthwise convolution operation result partition to generate a pointwise weighted partition, and performing an accumulation process in a depth dimension to generate an output partition; when the output partition meets operation criteria in the depth dimension, performing a pointwise offset operation on the output partition to generate and output a pointwise convolution operation result partition; and when the output partition does not meet the operation criteria in the depth dimension, configuring the output partition to be a previous output partition to operate next operation data.