A storage system manages correspondence relationships between physical addresses and logical addresses inside a storage device, as well as logical spaces provided by a plurality of storage devices, and when a determination is made as to whether first data and second data are stored in the same storage device in a case in which the first data and the second data are exchanged inside a logical space, and the determination is found to be affirmative, the storage device replaces the logical address corresponding to the first data with the logical address corresponding to the second data without changing the physical address of the physical area in which the first data is stored and the physical address of the physical area in which the second data is stored.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.

An accelerator is disclosed. The accelerator may include an on-chip memory to store a data from a database. The on-chip memory may include a first memory bank and a second memory bank. The first memory bank may store the data, which may include a first value and a second value. A computational engine may execute, in parallel, a command on the first value in the data and the command on the second value in the data in the on-chip memory. The on-chip memory may be configured to load a second data from the database into the second memory bank in parallel with the computation engine executing the command on the first value in the data and executing the command on the second value in the data.