Disclosed herein are an apparatus and method for extracting memory map information from firmware. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program retrieves memory-related data from firmware, sets a data structure by analyzing binary code based on the memory-related data, and retrieves a memory map structure from the firmware using the data structure.

A provisional page to be filled with data is allocated in an in-memory database system in which pages are loaded into memory and having associated physical disk storage a provisional page to be filled with data. Thereafter, the provisional page is filled with data. The provisional page is register after the provisional page has been filled with data such that consistent changes in the database are not required for the provisional page prior to the registering.

Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.

According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.

A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.

A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.