Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

A flash memory initialization method executed by a flash memory initialization device to initialize a flash memory device having a flash memory and a flash memory controller includes: determining an acceptable maximum number N of candidate addresses; determining a number M of different capacity sizes; classifying the candidate addresses into M portions; determining a difference value between two address values of any two adjacent addresses among the m-th portion of candidate addresses; determining multiple address values of the m-th portion of candidate addresses according to the difference value; and determining actual addresses of the m-th portion of candidate addresses according to the multiple address values; and controlling the flash memory controller to write the boot up information into at least one storage location corresponding to at least one of the m-th portion of candidate addresses according to the actual addresses.

A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.

The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

A system includes a printed circuit board (PCB) on which is disposed memory components and a processor disposed on the PCB and coupled between the memory components and a host memory controller. The processor comprises a memory channel network (MCN) memory controller to handle memory requests associated with the memory components; a local buffer; and a core coupled to the MCN memory controller and the local buffer. The core executes an operating system (OS) running a network software layer and a distributed computing framework; and an MCN driver to: receive a network packet from the network software layer; store the network packet in the local buffer; and assert a transmit polling field of the local buffer to signal to the host memory controller that the network packet is available for transmission to a host computing device.

A data storage device includes a storage including a buffer zone and a data zone and a controller for exchanging data with the storage by allocating at least one zone namespace (ZNS) in the data zone, a ZNS being a data storage region that is physically and logically divided and allocated to each of application programs driven in a host. The controller opens one or more sub buffer zones in the buffer zone, divides write data from the host into one or more segments respectively corresponding to sizes of the one or more sub buffer zones, buffers each of the one or more segments in a corresponding one of the one or more sub buffer zones, opens a ZNS corresponding to a length of the write data in the data zone, and migrates the one or more segments buffered in the sub buffer zones to the opened ZNS.

A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.