Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.

Techniques involve managing a storage space. In response to receiving an allocation request for allocating a storage space, a storage space size and a slice size are obtained. A first storage system and a second storage system are selected from multiple storage systems, the first storage system and the second storage system includes a first storage device group and a second storage device group respectively, and the first storage device group does not overlap the second storage device group. A first slice group and a second slice group is obtained from the first storage system and the second storage system respectively, on the basis of the size of the storage space and the size of the slice. A user storage system is built at least on the basis of the first slice group and the second slice group, so as to respond to the allocation request.

Embodiments are disclosed to mitigate the meltdown vulnerability by selectively using page table isolation. Page table isolation is enabled for 64-bit applications, so that unprivileged areas in the kernel address space cannot be accessed in user mode due to speculative execution by the processor. On the other hand, page table isolation is disabled for 32-bit applications thereby providing mapping into unprivileged areas in the kernel address space. However, speculative execution is limited to a 32-bit address space in a 32-bit application, and s access to unprivileged areas in the kernel address space can be inhibited.

Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.

A apparatus includes a storing region and an access controller. The storing region includes: a first area to which a value indicating one of first and second bit modes is set; a second area to which information indicating whether a third bit mode is enabled or disabled is set, the first and second bit modes specifying a bit length of addresses in a memory to first and second bit lengths, respectively, the third bit mode specifying the bit length to a third bit length greater than second bit length; and an address area to which an address in the first or second bit length is set. When the information in the second area indicates that the third bit mode is enabled, the access controller accesses the memory based on a concatenated address defined by concatenating the value set in the first area and the address set in the address area.

An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant pqe bits of the lower limit and the upper limit is derivable from the most significant pqe bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2.sup.x regions of size 2.sup.n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.

The present image processing apparatus mutually converts raster-order image data and block-order image data by dividing image data into a plurality of areas in units of bands, and performing reading-out and writing of the image data to one line memory in the units of bands of the division. The apparatus calculates, in the units of bands, an address increased amount, which is used for calculating an address to next write to or read out from, from an address that is a current processing target, calculates an address of a write destination when writing image data to the line memory and an address of a readout destination when reading-out image data from the line memory by adding the calculated address increased amount to an address value of a current processing target address.

A processing system includes a processor core for processing instructions and a memory that stores a page table set including an extended page table having an extended page table entry storing extended page table attributes associated with a physical memory page. The system receives a virtual address and translates the virtual address to a physical address for the physical memory page. One or more extended page attributes associated with the physical memory page are retrieved from the extended page table entry based on the virtual address.

An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.