A system includes memory and one or more processors programmed to operate a logical layer, a media link layer, and a slot layer. The logical layer is configured to send and receive object data to a host according to an object storage protocol. The media link layer is configured to map the object data to virtual media addresses. The slot layer is configured to map the virtual media addresses to physical addresses of data storage devices.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

The disclosure relates to a collecting method implemented by a first device including a first volatile memory, this first device interacting with a second device including a second non-volatile memory, the memories comprising objects each constituting an instance of an object-oriented language class. The method comprises an analysis of the objects by running through an object tree from the persistent roots; and on detecting that the analysis is finished, a collecting from the first and second memories for deleting each object that has not been analyzed during said analysis. This analysis in particular comprises, for each object: the identification of each reference pointing to another object; and the definition of a first or second type for each identified reference, this analysis continuing only along the references of the first type.

Disclosed are a storage device including a memory controller and a method of operating the memory controller. A storage device according to the technical idea of the present disclosure includes a write buffer for storing write data that is not grouped into a transaction, a non-volatile memory device including a journal buffer where journal logs are stored, a volatile memory device for temporarily storing first metadata, and a memory controller for updating the first metadata to the second metadata based on the journal log stored after the start of the checkpoint among the journal logs stored in the journal buffer.

An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.

Provided herein are a page buffer and a memory device having the same. The page buffer may include: a latch circuit comprising a first node configured to be set to a first level in response to a sense amplifier strobe signal when an operation of setting up a bit line is performed during a program operation of a semiconductor memory device; a current control circuit configured to supply an internal power to a current sensing node depending on a value of the first level of the first node; and a page buffer sensing circuit configured to couple the bit line to the current sensing node in response to a page buffer sensing signal and control a potential level of the bit line depending on a potential level of the page buffer sensing signal.

An allocation request for requesting allocation of a target virtual area with respect to target data issued to a system program includes a target ID corresponding to the target data. In response to the allocation request, whether or not the target ID is included in data map information is determined. When it is included in the data map information, the system program determines whether or not a target physical area is included in a storage apparatus. When the target physical area is included in the storage apparatus, the system program reserves a free area in a non-volatile memory as a target memory area, copies target data stored in the storage apparatus to the target memory area, changes the target physical area in the data map information to the target memory area, and writes an association between the target virtual area and the target memory area into the volatile memory.