An embodiment of an apparatus may include a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory, the circuitry to manage a portion of the memory as hidden memory outside a range of physical memory accessible by user applications, and control access to the hidden memory from the processor with hidden page tables. Other embodiments are disclosed and claimed.

An infrastructure for mapping between logic block addresses (LBAs) and physical block addresses (PBAs). A disclosed method includes: receiving a request the specifies an LBA; determining an applicable zone based on the LBA from a set of zones, wherein the set of zones expose an LBA address space of the storage device; identifying at least one tree from a set of trees having a root node associated with the applicable zone; traversing the at least one tree to identify a set of leaf nodes based on the LBA, wherein each leaf node points to an mpage; and determining corresponding PBA information for the LBA by examining mapping information contained in each mpage.

Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.

An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

A flash memory initialization method executed by a flash memory initialization device to initialize a flash memory device having a flash memory and a flash memory controller includes: determining an acceptable maximum number N of candidate addresses; determining a number M of different capacity sizes; classifying the candidate addresses into M portions; determining a difference value between two address values of any two adjacent addresses among the m-th portion of candidate addresses; determining multiple address values of the m-th portion of candidate addresses according to the difference value; and determining actual addresses of the m-th portion of candidate addresses according to the multiple address values; and controlling the flash memory controller to write the boot up information into at least one storage location corresponding to at least one of the m-th portion of candidate addresses according to the actual addresses.