Various embodiments include techniques for processing transactions via a computer system interconnect with a distributed firewall. The distributed firewall includes separate firewalls for various initiators of transactions and separate firewalls for various targets of those transactions. As a result, transactions proceed, for example, along the shortest path from the initiator to the target, rather than being routed through a centralized firewall. In addition, firewall transactions, for example, may be remapped such that initiators address the initiator firewalls and target firewalls via a unified address space, without having to maintain separate base addresses for each initiator firewall and target firewall. As a result, application programs, for example, can execute transactions with increased performance on a computer system as compared to prior approaches.

Provided are a storage system including a host and a storage device, and an operation method of the storage system. The storage device includes a memory controller and a memory device, where an operation method of the memory controller includes receiving from the host a first mode change request for a folder, which is a unit for managing at least one file, and a logical address of the at least one file, and in response to the first mode change request, rewriting to the memory device first data corresponding to the logical address in a second operating mode, and invalidating first data which is existing data already written to correspond to the logical address and the first data in a first operating mode, wherein the first mode change request sets a data operation speed to a high-speed mode for the at least one file included in the folder.

Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

A method for providing information to be stored includes computing a storable first secret for generating a random value based on a random function. The information to be stored is provided as a chunk which is divided into blocks each having an element. A storable second secret comprising a random element is computed. A tag is computed for each block such that the tag for the j-th block of the i-th chunk is computed using: an output of the random function, the j-th block, and a representation of the second secret. The information to be stored is provided together with an information tag comprising the computed tags of each block of each chunk.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

Technologies are described herein for remotely configuring multi-mode dual in-line memory modules (“multi-mode DIMMs”) using a firmware or a baseboard management controller (“BMC”). Technologies are also described for simultaneously initiating multiple commands for configuring multi-mode DIMMs using a BMC and for updating inventory data regarding multi-mode DIMMs stored by a BMC.

A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.