A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

An electronic-drum module for connection to one or more electronic-drum pads is provided. The module includes an electronic display; a first memory storing audio files for playback when the playback is triggered by a signal received from a pad; and one or more processors coupled to the display and the memory. The processors are configured receive an instruction to transfer a set of samples. The set of samples is associated with a priority-instruction and includes a first subset of samples and a second subset of samples. The processors are also configures to transfer the first subset of samples from a second memory to the first memory based on the priority-instruction before transferring the second subset of samples and to transfer the second subset of samples from the second memory to the first memory.

An electronic-drum module for connection to one or more electronic-drum pads is provided. The module includes an electronic display; a first memory storing audio files for playback when the playback is triggered by a signal received from a pad; and one or more processors coupled to the display and the memory. The processors are configured receive an instruction to transfer a set of samples. The set of samples is associated with a priority-instruction and includes a first subset of samples and a second subset of samples. The processors are also configures to transfer the first subset of samples from a second memory to the first memory based on the priority-instruction before transferring the second subset of samples and to transfer the second subset of samples from the second memory to the first memory.

A VPU and associated components include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators are used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer is included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU executes a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A VPU and associated components include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators are used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer is included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU executes a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

A computer-readable recording medium storing an information processing program for causing a computer to execute a process including: specifying an amount of first areas subjected to data update among a plurality of first areas that are contained in a cache storage area and allowed to be synchronized individually from each other with a nonvolatile storage area; and determining whether to individually synchronize the first areas subjected to the data update among the plurality of first areas with the nonvolatile storage area or collectively synchronize a second area that is formed by the plurality of first areas and allowed to be collectively synchronized with the nonvolatile storage area, with the nonvolatile storage area, based on the specified amount, a first processing time taken for synchronization between the first areas and the nonvolatile storage area, and a second processing time taken for synchronization between the second area and the nonvolatile storage area.

A computer-readable recording medium storing an information processing program for causing a computer to execute a process including: specifying an amount of first areas subjected to data update among a plurality of first areas that are contained in a cache storage area and allowed to be synchronized individually from each other with a nonvolatile storage area; and determining whether to individually synchronize the first areas subjected to the data update among the plurality of first areas with the nonvolatile storage area or collectively synchronize a second area that is formed by the plurality of first areas and allowed to be collectively synchronized with the nonvolatile storage area, with the nonvolatile storage area, based on the specified amount, a first processing time taken for synchronization between the first areas and the nonvolatile storage area, and a second processing time taken for synchronization between the second area and the nonvolatile storage area.