A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Data race detection in multi-threaded programs can be achieved by leveraging per-thread memory protection technology in conjunction with a custom dynamic memory allocator to protect shared memory objects with unique memory protection keys, allowing data races to be turned into inter-thread memory access violations. Threads may acquire or release the keys used for accessing protected memory objects at the entry and exit points of critical sections within the program. An attempt by a thread to access a protected memory object within a critical section without the associated key triggers a protection fault, which may be indicative of a data race.

A virtual machine deployment method, a virtual machine live migration method, a VMM upgrading method, a server, and a computer-readable storage medium are disclosed. The virtual machine deployment method includes: establishing mapping between a host virtual address (HVA) space for a post-upgrading virtual machine and a host physical address (HPA) space for a pre-upgrading virtual machine according to a mapping relationship between a HVA space for the pre-upgrading virtual machine and the HPA space for the pre-upgrading virtual machine. The post-upgrading virtual machine is deployed on a post-upgrading virtual machine monitor (VMM), and the post-upgrading virtual machine is identical in memory configuration with the pre-upgrading virtual machine running on a pre-upgrading VMM (S110).

A virtual machine deployment method, a virtual machine live migration method, a VMM upgrading method, a server, and a computer-readable storage medium are disclosed. The virtual machine deployment method includes: establishing mapping between a host virtual address (HVA) space for a post-upgrading virtual machine and a host physical address (HPA) space for a pre-upgrading virtual machine according to a mapping relationship between a HVA space for the pre-upgrading virtual machine and the HPA space for the pre-upgrading virtual machine. The post-upgrading virtual machine is deployed on a post-upgrading virtual machine monitor (VMM), and the post-upgrading virtual machine is identical in memory configuration with the pre-upgrading virtual machine running on a pre-upgrading VMM (S110).

A computing device having a tightly attached or closely attached hardware accelerator directly coupled with one or more processors for efficient uses of the hardware accelerator for executing specific functions are described. According to an embodiment, the hardware accelerator is instantiated inside the main processor unit and interfaces to a load-store unit (LS) using virtual addresses. The hardware accelerator instantiated inside the main processing unit (e.g., core) is referred to as a tightly attached hardware accelerator. In an alternative embodiment, the hardware accelerator is instantiated inside a cluster of processor cores. The hardware accelerator that is instantiated inside the cluster of processor cores but not inside a specific processor core is referred to as a closely attached hardware accelerator.

A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.

A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.

Methods, systems, and devices for power management techniques are described. A memory system may receive a command to exit a first power mode and enter a second power mode. The first power mode may have a lower power consumption than the second power mode. The memory system may determine whether a duration of an idle period associated with the first power mode satisfies a threshold based on receiving the command to exit the first power mode. The memory system may receive another command associated with executing a flush operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.