A computer program product for processing input/output (I/O) data is provided for performing a method that includes receiving a transport control word (TCW) including an indirect data address including a starting location of a transport mode indirect data address list (TIDAL) of storage addresses, the TIDAL including a plurality of entries configured as transport mode indirect data address words (TIDAWs). The method includes accessing an entry of the TIDAL, which includes: 1) based on the entry of the TIDAL indicating that the address is a data address, gathering data from a data storage location corresponding to the data address, and accessing a next entry of the TIDAL, and 2) based on the entry of the TIDAL indicating that the address is an address of a next entry of the TIDAL, obtaining the next entry of the TIDAL from another storage location that is located non-contiguously to the entry storage location.

The present disclosure provides a data transmission method and device. The data transmission method is used for transmitting data between an advanced reduced instruction set computing machine (ARM) and a field programmable logic gate array (FPGA) via an Inter-Integrated Circuit (IIC) bus, comprising the following steps: receiving, by the FPGA, communication data transmitted by the ARM via the IIC bus, wherein the communication data comprises first address data, first content data and N second content data, N being an integer greater than 0, the first content data and the N second content data being arranged in sequence, and the first address data being address data corresponding to the first content data; and generating, by the FPGA, second address data corresponding to each of the second content data according to the sequence of the N second content data and the first address data.

Systems, apparatuses, and methods related to extended memory microcode components for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can include a plurality of microcode components coupled to each of the plurality of computing devices and each comprise a set of microcode instructions. The example apparatus can further include a communication subsystem coupled to a host and to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, retrieve at least one of the set of microcode instructions, transfer a command and the at least one of the set of microcode instructions, and receive a result of performing the operation.

Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).

A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A data pipeline circuit includes an upstream interface circuit that receives sequential data and a downstream interface circuit that transfers the sequential data to a downstream circuit. A ready signal indicates the downstream circuit is ready to receive the sequential data. The data pipeline circuit includes a first data latch, a second data latch and a first status latch. The first data latch receives the sequential data. The first status latch generates an available signal that is asserted to indicate the second data latch is available to receive the sequential data. The second data latch receives the sequential data in response on the available signal being asserted and the ready signal indicating the downstream circuit is not ready to receive the sequential data on the data output. Limiting conditions in which the sequential data is stored in the second data latch significantly reduces power consumption of the data pipeline circuit.

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

A graph-based data flow control system includes a control plane system coupled to SCP subsystems. The control plane system identifies a workload, and identifies service(s) on the SCP subsystems for manipulting/exchanging data to perform the workload. The control plane system generates a respective SCP-local data flow control graph for each SCP subsystem that defines how their service(s) will manipulate/exchange data within that SCP subsystem, and generates inter-SCP data flow control graph(s) that define how service(s) provided by at least one SCP subsystem will manipulate/exchange data with service(s) provided by at least one other SCP subsystem. The control plane system then transmits each respective SCP-local data flow control graph to each of the SCP subsystems, and the inter-SCP data flow control graph(s) to at least one SCP subsystem, for use by the SCP subsystems in causing their service(s) to manipulate/exchange data to perform the workload.

The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).