Bandwidth control can be provided for input/output channels according to some aspects described herein. In one example, a system can detect an input/output (I/O) request transmitted by a software application. In response to detecting the I/O request, the system can determine a bandwidth group that corresponds to an I/O channel associated with the I/O request. The system can then determine whether bandwidth consumption of the bandwidth group exceeds a predefined bandwidth limit. If so, the system can execute a predefined policy assigned to the I/O channel for handling the I/O request.

Embodiments of systems and methods for platform framework arbitration are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: provide, from a platform framework to an arbitration object via an Application Programming Interface (API), a plurality of runtime objects; receive, by the platform framework from the arbitration object via the API, an indication of an arbitration result with respect to the plurality of objects; and convey, from the platform framework to a participant via the API, the indication of the arbitration result.

Embodiments of systems and methods for platform framework telemetry are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive telemetry data at a telemetry service from at least one producer registered with a platform framework via an Application Programming Interface (API); receive a request for at least a subset of the telemetry data from a consumer registered with the platform framework via the API; and transmit the subset of the telemetry data to the consumer.

Embodiments of systems and methods for standby operation in a platform framework are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: identify an application registered with a platform framework via an Application Programming Interface (API); and at least one of: in response to the identification matching any entry in a whitelist, put the application in a throttled state during standby operation of the IHS; or in response to the identification not matching any entry in the whitelist, put the application in a suspended state during standby operation of the IHS.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.