A storage device is provided that allows a controller to directly access bytes of data in data latches connected to memory, as opposed to through controller RAM. The storage device may include a memory, a plurality of data latches connected to the memory, and a controller coupled to each of the data latches. The controller is configured to access one or more bytes of decoded data in one or more of the data latches. For instance, the controller may provide a command including an address for data in the memory, and may process one or more bytes of the data in at least one of the data latches in response to the command. The controller may also store a mapping of addresses for each of the word lines, including the address provided in the command. As a result, operation latency may be reduced and controller RAM savings achieved.

An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed. An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.

An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.

Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

A semiconductor device capable of executing a plurality of tasks in real time and improving performances is provided. The semiconductor device comprises a plurality of processors and a plurality of DMA controllers as master, a plurality of memory ways as slave, and a real-time schedule unit for controlling the plurality of masters such that the plurality of tasks are executed in real time. The real-time schedule unit RTSD uses the memory access monitor circuit and the data determination register to determine whether or not the input data of the task has been determined, and causes the task determined to have the input data determined to have been determined to be executed preferentially.

Examples herein relate to a solid state drive that includes a media, a processing system, and a media command arbiter configured to permit execution of a specific allocation of storage and compute commands based on a configuration, wherein the media command arbiter is to transfer commands to the media based on the configuration. The media can be locally connected to a compute engine processing system that is configurable to perform computations on data stored in the media. The configuration can indicate a number of compute commands and storage commands that are permitted to be performed over a period of time or media bandwidth allocated to compute commands and storage commands. The processing system can include an inference engine that performs one or more of: data pattern recognition, image recognition, augmented reality overlay applications, face recognition, object recognition, or voice recognition, language translation.

A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.