A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

Provided are a method and an apparatus for controlling power consumption, a board, an electronic device and a storage medium. The method is applied to a board, and the board includes a dynamic random memory. The method includes: obtaining a data flow of the board; and controlling an active bandwidth of the dynamic random memory according to the data flow.

NUMA-aware reader-writer locks may leverage lock cohorting techniques that introduce a synthetic level into the lock hierarchy (e.g., one whose nodes do not correspond to the system topology). The synthetic level may include a global reader lock and a global writer lock. A writer thread may acquire a node-level writer lock, then the global writer lock, and then the top-level lock, after which it may access a critical section protected by the lock. The writer may release the lock (if an upper bound on consecutive writers has been met), or may pass the lock to another writer (on the same node or a different node, according to a fairness policy). A reader may acquire the global reader lock (whether or not node-level reader locks are present), and then the top-level lock. However, readers may only hold these locks long enough to increment reader counts associated with them.

A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

A method for self-moderating bus arbitration for access to a common bus is provided. The method may include receiving, by a bus arbiter, a request from a master device, wherein the received request includes a priority value set by the master device. The method may also include identifying the priority value from the received transaction request. The method may then include determining an insertion point within a priority table based on comparing the identified priority value to a table entry priority value associated with each table entry within the priority table. The method may further include inserting a new entry into the priority table based on the determined insertion point. The method may also include identifying a highest priority entry within the priority table. The method may then include serving the identified highest priority entry.

A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

An electro-optic module provides electro-optic signal drivers formed upon a semiconductor carrier having electrically conducting traces and passive circuit network filtering elements of electroceramic material with the electro-optic signal drivers being in electrical communication with the passive circuit elements and interface the module within a larger computing or communications system.

Power regulation in an integrated memory assembly having control semiconductor dies and memory semiconductor is disclosed herein. A master control die regulates power usage by the integrated memory assembly. Each control die reports information about its expected power usage to the master control die. The master control die determines a plan that meets a power criterion for the integrated memory assembly. The plan may maximize the power usage in each time period, while staying within a power budget. The plan can include selecting which of the memory dies perform a memory operation (or phase of a memory operation) during a given time period. The master control die may send a die scheduling plan to each of the other control dies. Each die scheduling plan indicates when memory operations and/or phases of memory operations are to be performed.