According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

A non-volatile storage system includes: a host and a storage device. The host includes a submission queue memory, a completion queue memory, and a read/write data memory, and the storage device includes: a controller configured to concurrently communicate with the read/write data memory and with at least one of the submission queue memory and the completion queue memory; and a memory device configured to communicate with the controller.

A non-volatile storage system includes: a host and a storage device. The host includes a submission queue memory, a completion queue memory, and a read/write data memory, and the storage device includes: a controller configured to concurrently communicate with the read/write data memory and with at least one of the submission queue memory and the completion queue memory; and a memory device configured to communicate with the controller.

An electronic device comprises: a memory management module; a processor operatively connected to the memory management module; and a memory controlled by the memory management module and operatively connected to the processor. The memory is configured to store instructions which, when executed, cause the processor to: execute at least one process, identify a rate at which the at least one process is terminated, based on a preconfigured first cycle, determine a number of times the identified rate exceeds a first threshold value, and based on a determination that the number of times the identified rate exceeds the first threshold value is greater than a second threshold value, reboot the electronic device.

An electronic device includes a CPU that executes the process execution program to function as a plurality of process execution units as threads and an execution control unit. The plurality of process execution units use the CPU to execute a process. The execution control unit controls executing of the process by the plurality of process execution units. The execution control unit sets a CPU usage priority level for each of the plurality of process execution units. The execution control unit changes the CPU usage priority level of the job of a type other than a specific type to a priority level that is equal to or less than a specific priority level, when the job of the specific type and the job of the type other than the specific type are simultaneously executed.

An electronic device includes a CPU that executes the process execution program to function as a plurality of process execution units as threads and an execution control unit. The plurality of process execution units use the CPU to execute a process. The execution control unit controls executing of the process by the plurality of process execution units. The execution control unit sets a CPU usage priority level for each of the plurality of process execution units. The execution control unit changes the CPU usage priority level of the job of a type other than a specific type to a priority level that is equal to or less than a specific priority level, when the job of the specific type and the job of the type other than the specific type are simultaneously executed.

Methods, systems, and devices for a data circuit for a low swing data bus are described. An apparatus may include a data bus that may transfer data at a first voltage different than a second voltage that is associated with one or more components of the memory array. A transistor, coupled with the data bus, may receive the second voltage and send a third voltage. A first in first out (FIFO), coupled with the transistor, may receive the third voltage from the transistor. The FIFO circuit may include one or more precharge components that drive an input voltage of the FIFO circuit to the second voltage associated with the one or more components of the memory array based on receiving the third voltage.

Methods, systems, and devices for a data circuit for a low swing data bus are described. An apparatus may include a data bus that may transfer data at a first voltage different than a second voltage that is associated with one or more components of the memory array. A transistor, coupled with the data bus, may receive the second voltage and send a third voltage. A first in first out (FIFO), coupled with the transistor, may receive the third voltage from the transistor. The FIFO circuit may include one or more precharge components that drive an input voltage of the FIFO circuit to the second voltage associated with the one or more components of the memory array based on receiving the third voltage.

A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.

A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.