In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a processor, a first interrupt source configured to generate a first non-secure interrupt, and an interrupt blocking unit configured to block the first non-secure interrupt responsive to the processor operating in a secure state.

One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a processor, a first interrupt source configured to generate a first non-secure interrupt, and an interrupt blocking unit configured to block the first non-secure interrupt responsive to the processor operating in a secure state.

A method, computer program product, and computing system for assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores. A second set of interrupts may be assigned for processing by a second set of CPU cores. The first set of interrupts may be processed using the first set of CPU cores. The second set of interrupts may be converted to a set of polling operations, thus defining a set of converted polling operations. The set of converted polling operations may be processed using the second set of CPU cores.

A method, computer program product, and computing system for assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores. A second set of interrupts may be assigned for processing by a second set of CPU cores. The first set of interrupts may be processed using the first set of CPU cores. The second set of interrupts may be converted to a set of polling operations, thus defining a set of converted polling operations. The set of converted polling operations may be processed using the second set of CPU cores.

An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Upon receiving an interrupt request via any one from among multiple first interrupt signal lines, a serializer identifies an error device which is one device from among the multiple devices that has transmitted the interrupt request and transmits the identification number of the error device to a deserializer. Furthermore, the serializer reads status information from the error device via a first interface and transmits the status information of the error device to the deserializer. The deserializer is structured to store the identification number of the error device and the status information in its internal register, and of transmitting an interrupt request to a controller via a second interrupt signal line. The deserializer transmits the identification number of the error device and the status information to the controller in response to a read command received from the controller.

Upon receiving an interrupt request via any one from among multiple first interrupt signal lines, a serializer identifies an error device which is one device from among the multiple devices that has transmitted the interrupt request and transmits the identification number of the error device to a deserializer. Furthermore, the serializer reads status information from the error device via a first interface and transmits the status information of the error device to the deserializer. The deserializer is structured to store the identification number of the error device and the status information in its internal register, and of transmitting an interrupt request to a controller via a second interrupt signal line. The deserializer transmits the identification number of the error device and the status information to the controller in response to a read command received from the controller.