In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.

A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.

A control method for an optical transceiver includes interrupting internal repetitive internal processing in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data. The method sets a processing mode of the interrupt process to a first processing mode when a processing time necessary to execute the interrupt process and one cycle of the repetitive processing is shorter than a threshold value, and to a second processing mode when the processing time necessary to execute the interrupt process and one cycle of the repetitive processing is longer than the threshold value. In the first mode, the interrupt process stores first monitoring data read out from a memory unit in a transmission register, stops the stretching of a clock signal, and subsequently reads out second monitoring data from the memory unit to follow the first monitoring data. In the second mode, the interrupt process stores the first monitoring data read out from the memory unit in the transmission register, reads out the second monitoring data from the memory unit, and subsequently stops the stretching of the clock signal.

A control method for an optical transceiver includes interrupting internal repetitive internal processing in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data. The method sets a processing mode of the interrupt process to a first processing mode when a processing time necessary to execute the interrupt process and one cycle of the repetitive processing is shorter than a threshold value, and to a second processing mode when the processing time necessary to execute the interrupt process and one cycle of the repetitive processing is longer than the threshold value. In the first mode, the interrupt process stores first monitoring data read out from a memory unit in a transmission register, stops the stretching of a clock signal, and subsequently reads out second monitoring data from the memory unit to follow the first monitoring data. In the second mode, the interrupt process stores the first monitoring data read out from the memory unit in the transmission register, reads out the second monitoring data from the memory unit, and subsequently stops the stretching of the clock signal.

A microcontroller includes an event-detection circuit, a protection-control circuit, a digital-to-analog converter, a digital-to-analog conversion interface controller, a trigger-event controller, and a central processing unit. The event-detection circuit detects a sudden event, and correspondingly outputs an interrupt notification and a protection-enable signal. The protection-control circuit receives the protection-enable signal, and correspondingly outputs a protection-execution signal. The digital-to-analog conversion interface controller receives the protection-execution signal, stops updating the received input data, and stops outputting the acknowledgement signal. The trigger-event controller determines whether to set the conversion parameters of the digital-to-analog conversion interface controller according to the acknowledgement signal. The central processing unit determines and outputs the conversion parameters to the trigger-event controller, and receives the interrupt notification to eliminate the sudden event.

A microcontroller includes an event-detection circuit, a protection-control circuit, a digital-to-analog converter, a digital-to-analog conversion interface controller, a trigger-event controller, and a central processing unit. The event-detection circuit detects a sudden event, and correspondingly outputs an interrupt notification and a protection-enable signal. The protection-control circuit receives the protection-enable signal, and correspondingly outputs a protection-execution signal. The digital-to-analog conversion interface controller receives the protection-execution signal, stops updating the received input data, and stops outputting the acknowledgement signal. The trigger-event controller determines whether to set the conversion parameters of the digital-to-analog conversion interface controller according to the acknowledgement signal. The central processing unit determines and outputs the conversion parameters to the trigger-event controller, and receives the interrupt notification to eliminate the sudden event.

A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.