An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

The present technology relates to an information processing system, information processing method, and information processing device capable of reducing load on an information processing unit in a case where data is shared among a plurality of information processing devices. There are included a first information processing device that controls DMA on the basis of a transfer parameter used for controlling transfer of data, and a second information processing device that communicates with the first information processing device, and controls DMA on the basis of the transfer parameter, in which the first information processing device generates the transfer parameter used for controlling reception of transfer data, and transmits the transfer parameter to the second information processing device, and the second information processing device controls reception of the transfer data from the first information processing device on the basis of the transfer parameter received from the first information processing device. The present technology can be applied to, for example, an apparatus including a multiprocessor system.

The present technology relates to an information processing system, information processing method, and information processing device capable of reducing load on an information processing unit in a case where data is shared among a plurality of information processing devices. There are included a first information processing device that controls DMA on the basis of a transfer parameter used for controlling transfer of data, and a second information processing device that communicates with the first information processing device, and controls DMA on the basis of the transfer parameter, in which the first information processing device generates the transfer parameter used for controlling reception of transfer data, and transmits the transfer parameter to the second information processing device, and the second information processing device controls reception of the transfer data from the first information processing device on the basis of the transfer parameter received from the first information processing device. The present technology can be applied to, for example, an apparatus including a multiprocessor system.

An information processing device includes a field programmable gate array configured to store route information in flow control, and forward packets according to the route information; one or more memories configured to store a flow cache that includes at least a part of the route information; and one or more processors coupled to the one or more memories and the one or more processors configured to divide the route information into a plurality of division areas; and acquire hit information extracted from each of the entries in a first division area of the plurality of division areas to delete a part of entries of the flow cache stored in the one or more memories, the first division area including flows whose number is greater than a threshold value.

An information processing device includes a field programmable gate array configured to store route information in flow control, and forward packets according to the route information; one or more memories configured to store a flow cache that includes at least a part of the route information; and one or more processors coupled to the one or more memories and the one or more processors configured to divide the route information into a plurality of division areas; and acquire hit information extracted from each of the entries in a first division area of the plurality of division areas to delete a part of entries of the flow cache stored in the one or more memories, the first division area including flows whose number is greater than a threshold value.

A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.

A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.

An electronic device includes a transaction host, first and second peripherals, memory, an access control register, and first and second access controllers. The memory stores access control identifier management instructions, a first task related to the first peripheral, and a first bitmask indicating respective access settings for the first and second peripherals for performing the first task. The access control register includes a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The transaction host executes the access control identifier management instructions to program the first and second access control identifiers based on the first bitmask, and subsequently executes the first task. The first and second access controllers control access to the first and second peripherals, respectively, based on the respective first and second access control identifiers programmed based on the first bitmask.

An electronic device includes a transaction host, first and second peripherals, memory, an access control register, and first and second access controllers. The memory stores access control identifier management instructions, a first task related to the first peripheral, and a first bitmask indicating respective access settings for the first and second peripherals for performing the first task. The access control register includes a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The transaction host executes the access control identifier management instructions to program the first and second access control identifiers based on the first bitmask, and subsequently executes the first task. The first and second access controllers control access to the first and second peripherals, respectively, based on the respective first and second access control identifiers programmed based on the first bitmask.