An integrated circuit is provided, which includes: a processor, a general interrupt controller, and a bus master. The bus master includes: a bus-control circuit and a polling circuit, which is configured to detect whether an interrupt signal of the sensing device is asserted. In response to the polling circuit detecting that the interrupt signal is asserted, the bus-control circuits fetches each task stored in a task queue of a memory in sequence, and performs one or more data-transfer operations corresponding to each task to obtain sensor data from the sensing device. In response to a task-completion signal of the tasks generated by the bus-control circuit, the general interrupt controller generates an interrupt request signal. In response to the interrupt request signal, the processor reports a sensor event using the sensor data obtained by the data-transfer operations corresponding to each task.

A method includes receiving, by a virtual machine running on a computing system, a public cryptographic key associated with a peripheral device of the computing system. The method further includes, responsive to validating the public cryptographic key, encrypting a cryptographic nonce value with the public cryptographic key. The cryptographic nonce value encrypted with the public cryptographic key is transmitted to the peripheral device. The method further includes using a shared cryptographic key generated from the cryptographic nonce value to access contents of a direct memory access (DMA) buffer utilized by the peripheral device.

A transfer device (230) for communicating with a first processing device (110 or 210) and a second processing device (210 or 110) by PCIe is provided. The transfer device (230) is provided with a direct memory access controller (DMAC) (233) for controlling a data transfer from a first memory (120 or 220) of the first processing device to a second memory (220 or 120) of the second processing device; a first transmission descriptor controller (235 or 237) for acquiring, from the first processing device, information relating to a first memory address in the first memory at which the data to be transferred is stored; and a first reception descriptor controller (234 or 236) for acquiring, from the second processing device, information relating to a second memory address in the second memory at which the data to be transferred should be stored.

A transfer device (230) for communicating with a first processing device (110 or 210) and a second processing device (210 or 110) by PCIe is provided. The transfer device (230) is provided with a direct memory access controller (DMAC) (233) for controlling a data transfer from a first memory (120 or 220) of the first processing device to a second memory (220 or 120) of the second processing device; a first transmission descriptor controller (235 or 237) for acquiring, from the first processing device, information relating to a first memory address in the first memory at which the data to be transferred is stored; and a first reception descriptor controller (234 or 236) for acquiring, from the second processing device, information relating to a second memory address in the second memory at which the data to be transferred should be stored.

A RFID system includes an RFID controller incorporating a serial bus master coupled via a serial bus to a serial bus slave device, whereby the RFID controller controls power supply and/or power mode of the salve device in order that the slave device is powered and able to communicate with the RFID controller in response to RFID commands received from an RFID reader, and unpowered or in a low power mode otherwise.

A RFID system includes an RFID controller incorporating a serial bus master coupled via a serial bus to a serial bus slave device, whereby the RFID controller controls power supply and/or power mode of the salve device in order that the slave device is powered and able to communicate with the RFID controller in response to RFID commands received from an RFID reader, and unpowered or in a low power mode otherwise.

Systems and methods are provided for detection of device functions asserting a spurious interrupt. An example method includes detecting, by a central processing unit executing an operating system, a spurious hardware interrupt signal from a device function, wherein a plurality of device functions include the device function, determining an Interrupt Request (IRQ) value from the spurious hardware interrupt signal, wherein the plurality of device functions share the IRQ value, and scanning each of the plurality of device functions to determine the device function generated the spurious hardware interrupt signal.

The present disclosure provides methods and apparatus for rapid interrupt look-ups for interrupts stored in memory. One embodiment relates to a method for providing interrupt lookups for a plurality of interrupt status vectors stored in random access memory on an integrated circuit. The plurality of interrupt status vectors in the random access memory are scanned to find activated interrupt status vectors that changed from null to non-null and dismissed interrupt status vectors that changed from non-null to null. A linked search list is maintained in the random access memory by inserting memory addresses of the activated interrupt status vectors into the linked search list and removing memory addresses of the dismissed interrupt status vectors from the linked search list. Interrupt status vectors for currently active interrupts are looked-up by transversing the linked search list in the random access memory. Other embodiments, aspects and features are also disclosed herein.

A system including a bus, a buffer, a bridge and a module. The bus is connected to multiple devices. The buffer is connected to the bus. The buffer is configured to transfer data to or receive the data from one or more of the devices, forward the data during a forwarding mode, and receive the data during a gathering mode. The module is configured to determine whether a first condition and/or a second condition exist. Based on whether the first condition exists, the module is configures the bridge to transfer the data from the buffer to a host system or transitions the buffer from the gathering mode to the forwarding mode to forward the data from the buffer to the one or more of the devices. Based on whether the second condition exists, the module is configured to transition the buffer from the forwarding mode to the gathering mode.

A system including a bus, a buffer, a bridge and a module. The bus is connected to multiple devices. The buffer is connected to the bus. The buffer is configured to transfer data to or receive the data from one or more of the devices, forward the data during a forwarding mode, and receive the data during a gathering mode. The module is configured to determine whether a first condition and/or a second condition exist. Based on whether the first condition exists, the module is configures the bridge to transfer the data from the buffer to a host system or transitions the buffer from the gathering mode to the forwarding mode to forward the data from the buffer to the one or more of the devices. Based on whether the second condition exists, the module is configured to transition the buffer from the forwarding mode to the gathering mode.