A transfer device (230) for communicating with a first processing device (110 or 210) and a second processing device (210 or 110) by PCIe is provided. The transfer device (230) is provided with a direct memory access controller (DMAC) (233) for controlling a data transfer from a first memory (120 or 220) of the first processing device to a second memory (220 or 120) of the second processing device; a first transmission descriptor controller (235 or 237) for acquiring, from the first processing device, information relating to a first memory address in the first memory at which the data to be transferred is stored; and a first reception descriptor controller (234 or 236) for acquiring, from the second processing device, information relating to a second memory address in the second memory at which the data to be transferred should be stored.

A processing device in a memory sub-system iteratively processes input/output (I/O) operations corresponding to a plurality of logical devices associated with a memory device. Tor each of the plurality of logical devices, the processing includes identifying a current logical device, determining one or more I/O operations in queue for the current logical device, and determining a number of operation credits associated with the current logical device. The number of credits is based at least in part on a set of quality of service (QoS) parameters for the current logical device. The processing further includes responsive to determining that the number of operation credits satisfies a threshold condition, performing the one or more I/O operations for the current logical device and identifying a subsequent logical device of the plurality of logical devices.

A processing device in a memory sub-system iteratively processes input/output (I/O) operations corresponding to a plurality of logical devices associated with a memory device. Tor each of the plurality of logical devices, the processing includes identifying a current logical device, determining one or more I/O operations in queue for the current logical device, and determining a number of operation credits associated with the current logical device. The number of credits is based at least in part on a set of quality of service (QoS) parameters for the current logical device. The processing further includes responsive to determining that the number of operation credits satisfies a threshold condition, performing the one or more I/O operations for the current logical device and identifying a subsequent logical device of the plurality of logical devices.

A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.

A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.

The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).

The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).

A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.