A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Bandwidth consumption for IO paths between a storage system and host may be managed. It may be determined whether there is congestion on a front-end port (FEP) link. For example, the storage system may monitor for a notification from the switch in accordance with a Fibre Channel (FC) protocol. If a notification is received indicating congestion on an FEP link, the bandwidth thresholds (BWTs) for one or more IO paths between the storage system and one or more hosts that include the FEP link may be reduced. The host port BWTs may continue to be reduced until a congestion notification communication has not been received for a predetermined amount of time, in response to which the host port BWTs for one or more host port links on IO paths that include the FEP link may be increased. Similar techniques may be employed for an FEP link determined to be faulty.

Bandwidth consumption for IO paths between a storage system and host may be managed. It may be determined whether there is congestion on a front-end port (FEP) link. For example, the storage system may monitor for a notification from the switch in accordance with a Fibre Channel (FC) protocol. If a notification is received indicating congestion on an FEP link, the bandwidth thresholds (BWTs) for one or more IO paths between the storage system and one or more hosts that include the FEP link may be reduced. The host port BWTs may continue to be reduced until a congestion notification communication has not been received for a predetermined amount of time, in response to which the host port BWTs for one or more host port links on IO paths that include the FEP link may be increased. Similar techniques may be employed for an FEP link determined to be faulty.

A system includes a processor configured to wirelessly broadcast a message obtained from a first originating vehicle BUS or controller, following a determination that the message was on a pre-approved list for broadcast and having encrypted the message utilizing a temporary random key generated for a message session. The system may include vehicle controllers, a gateway module, and vehicle BUSSES connecting the system controllers to the gateway module. The gateway module may include a memory storing a list of pre-approved message types and corresponding source types, and a processor configured to receive a message from one of the vehicle controllers over one of the vehicle BUSSES to determine if a message type and source type of the received message matches an element of the list.

A system includes a processor configured to wirelessly broadcast a message obtained from a first originating vehicle BUS or controller, following a determination that the message was on a pre-approved list for broadcast and having encrypted the message utilizing a temporary random key generated for a message session. The system may include vehicle controllers, a gateway module, and vehicle BUSSES connecting the system controllers to the gateway module. The gateway module may include a memory storing a list of pre-approved message types and corresponding source types, and a processor configured to receive a message from one of the vehicle controllers over one of the vehicle BUSSES to determine if a message type and source type of the received message matches an element of the list.

Bus system comprising a first bus and a second bus, wherein the first bus is connected to the second bus through a bridge and a multiplexer. A first master has access to the second bus via the first bus, the bridge and the multiplexer. A second master has access to the second bus via the multiplexer. The bridge comprises an arbitration unit which is arranged to allow both a first master and a second master access to the second bus in such a way that no access is disturbed or lost.