G06F13/362

DATA COMMUNICATION METHOD, MASTER DEVICE AND SYSTEM

Disclosed by the present application are a method, master device and system for data communication. The method comprises: initiating a communication signal to an interface in an interface module; when response information from a slave device connected in the interface is received, adding physical ID information of the interface into an online queue, wherein the probability that interfaces in the online queue is subsequently initiated by the communication signal is higher than that of interfaces in an idle queue; and receiving data information transmitted by the slave device in the interface. The data communication master device of the present application comprises a communication signal initiation unit, an online interface identification unit and a data information receiving unit corresponding to the implementation of steps of the described method. Therefore, the communication network for multiple slave devices and a master device has high communication efficiency.

DATA COMMUNICATION METHOD, MASTER DEVICE AND SYSTEM

Disclosed by the present application are a method, master device and system for data communication. The method comprises: initiating a communication signal to an interface in an interface module; when response information from a slave device connected in the interface is received, adding physical ID information of the interface into an online queue, wherein the probability that interfaces in the online queue is subsequently initiated by the communication signal is higher than that of interfaces in an idle queue; and receiving data information transmitted by the slave device in the interface. The data communication master device of the present application comprises a communication signal initiation unit, an online interface identification unit and a data information receiving unit corresponding to the implementation of steps of the described method. Therefore, the communication network for multiple slave devices and a master device has high communication efficiency.

Method for Initializing a Security Bus in a Master-Slave System
20220358252 · 2022-11-10 ·

A method initializes a security bus in a security bus system. The method includes scanning the security bus in order to identify slave units connected to the security bus, and determining, for each identified slave unit, whether the slave unit is a standard slave unit or a slave unit that itself provides input data for the security controller. The method further includes assigning, for each identified slave unit, an address to the slave unit. If the slave unit is a standard slave unit, then the slave unit is automatically assigned a communication address. If the slave unit is a slave unit that itself provides input data for the security controller, then the slave unit is automatically assigned a communication address and additionally a security address. The method also includes storing the addresses assigned to the identified slave units in order to initialize the security bus.

Method for Initializing a Security Bus in a Master-Slave System
20220358252 · 2022-11-10 ·

A method initializes a security bus in a security bus system. The method includes scanning the security bus in order to identify slave units connected to the security bus, and determining, for each identified slave unit, whether the slave unit is a standard slave unit or a slave unit that itself provides input data for the security controller. The method further includes assigning, for each identified slave unit, an address to the slave unit. If the slave unit is a standard slave unit, then the slave unit is automatically assigned a communication address. If the slave unit is a slave unit that itself provides input data for the security controller, then the slave unit is automatically assigned a communication address and additionally a security address. The method also includes storing the addresses assigned to the identified slave units in order to initialize the security bus.

SYSTEM DECODER FOR TRAINING ACCELERATORS

There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

SYSTEM DECODER FOR TRAINING ACCELERATORS

There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

COMPUTATIONAL STORAGE WITH PRE-PROGRAMMED SLOTS USING DEDICATED PROCESSOR CORE
20220350604 · 2022-11-03 ·

The technology disclosed herein provides a method including determining one or more dedicated computations storage programs (CSPs) used in a target market for a computational storage device, storing the dedicated CSPs in one or more pre-programmed computing instruction set (CIS) slots in the computational storage device, translating one or more instructions of the dedicated CSPs for processing using a native processor, loading one or more instructions of programmable CSPs to a CSP processor implemented within an application specific integrated circuit (ASIC) of the computational storage device, and processing the one or more instructions of the programmable CSPs using the CSP processor.

COMPUTATIONAL STORAGE WITH PRE-PROGRAMMED SLOTS USING DEDICATED PROCESSOR CORE
20220350604 · 2022-11-03 ·

The technology disclosed herein provides a method including determining one or more dedicated computations storage programs (CSPs) used in a target market for a computational storage device, storing the dedicated CSPs in one or more pre-programmed computing instruction set (CIS) slots in the computational storage device, translating one or more instructions of the dedicated CSPs for processing using a native processor, loading one or more instructions of programmable CSPs to a CSP processor implemented within an application specific integrated circuit (ASIC) of the computational storage device, and processing the one or more instructions of the programmable CSPs using the CSP processor.

Bus system and method for allocating addresses to a plurality of bus subscribers in a bus system
11487686 · 2022-11-01 · ·

A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Bus system and method for allocating addresses to a plurality of bus subscribers in a bus system
11487686 · 2022-11-01 · ·

A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.