A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

An AXI bus structure and a chip system. The AXI bus structure includes: at least two master functional unit groups, each of which including at least two master functional units; at least two first routing units, being in one-to-one correspondence with the at least two first routing units, and each of the first routing units being respectively connected to each master functional unit of the corresponding master functional unit group by an AXI bus; at least two second routing units, each second routing unit being respectively connected to each first routing unit by an AXI bus; at least two slave functional unit groups, each slave functional unit group including at least two second slave functional units, which being in one-to-one correspondence with the second routing units, and each second routing unit being respectively connected to each slave functional unit of the corresponding slave functional unit group by an AXI bus.

An AXI bus structure and a chip system. The AXI bus structure includes: at least two master functional unit groups, each of which including at least two master functional units; at least two first routing units, being in one-to-one correspondence with the at least two first routing units, and each of the first routing units being respectively connected to each master functional unit of the corresponding master functional unit group by an AXI bus; at least two second routing units, each second routing unit being respectively connected to each first routing unit by an AXI bus; at least two slave functional unit groups, each slave functional unit group including at least two second slave functional units, which being in one-to-one correspondence with the second routing units, and each second routing unit being respectively connected to each slave functional unit of the corresponding slave functional unit group by an AXI bus.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

Systems, methods, circuits, and devices for data protection are provided. In one example, a data processing device incudes a Physical Unclonable Function (PUF) source that is configured to generate PUF values, a bus, a plurality of bus access components that are configured to access the bus, and a masking information generation circuit. The masking information generation circuit is configured to generate masking information for at least one pair of bus access components using at least one PUF value and to transmit said information to the bus access components. The pair is configured in such a way that one bus access component masks the data according to the masking information generated for the pair before the data is sent over the bus and the other bus access component de-masks the data received over the bus according to the masking information generated for the pair.

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.