A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

In one embodiment, a system for managing communication connections in a virtualization environment, comprises a plurality of host machines implementing a virtualization environment, wherein each of the host machines comprises a hypervisor, at least one user virtual machine (UVM), a connection agent, and an I/O controller; and a virtual disk comprising a plurality of storage devices, the virtual disk being accessible by all of the I/O controllers, wherein the I/O controllers conduct I/O transactions with the virtual disk based on I/O requests received from the UVMs, and wherein, for each of the host machines: each of the UVMs on the host machine sends its respective I/O requests to a selected one of the I/O controllers, and for each of the UVMs on the host machine, the connection agent on the host machine selected one of the I/O controllers for the UVM based on a list of the available I/O controllers.

In one embodiment, a system for managing communication connections in a virtualization environment, comprises a plurality of host machines implementing a virtualization environment, wherein each of the host machines comprises a hypervisor, at least one user virtual machine (UVM), a connection agent, and an I/O controller; and a virtual disk comprising a plurality of storage devices, the virtual disk being accessible by all of the I/O controllers, wherein the I/O controllers conduct I/O transactions with the virtual disk based on I/O requests received from the UVMs, and wherein, for each of the host machines: each of the UVMs on the host machine sends its respective I/O requests to a selected one of the I/O controllers, and for each of the UVMs on the host machine, the connection agent on the host machine selected one of the I/O controllers for the UVM based on a list of the available I/O controllers.

A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.

A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.

A method for cross enclave information control is provided including causing the transmission of an information packet between a plurality of information enclaves on a communication bus. A respective information enclave of the plurality of information enclaves is associated with a respective enclave guard of a plurality of enclave guards. The method also includes controlling the entrance and exit of the information packet into and out of the respective information enclave by the respective enclave guard.

A method for cross enclave information control is provided including causing the transmission of an information packet between a plurality of information enclaves on a communication bus. A respective information enclave of the plurality of information enclaves is associated with a respective enclave guard of a plurality of enclave guards. The method also includes controlling the entrance and exit of the information packet into and out of the respective information enclave by the respective enclave guard.

A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.