The disclosed computer-implemented method may include (1) receiving, by a first internal physical processor of an accelerator from an external processor, a request to access a result of executing a sensitive application within a secure execution zone of the accelerator having (a) a second internal physical processor and (b) physical memory accessible to the second internal physical processor but inaccessible to the first internal physical processor and the external processor, (2) executing, by the second internal physical processor within the secure execution zone, the sensitive application from the physical memory to generate the result, (3) making, by the second internal physical processor, the result accessible outside of the secure execution zone, and (4) relaying, by the first internal physical processor, the result to the external processor. Various other methods, systems, and computer-readable media are also disclosed.

Framework for network bypass is disclosed herein. Exemplary network bypass apparatus may include a relay, a first connection interface connectable to a network device, a second connection interface connectable to a first communication device, and a third connection interface connectable to a second communication device. The network bypass apparatus may further include a housing enclosing the relay and the first, second and third connection interfaces, wherein the relay communicatively couples the first connection interface and the third connection interface while communicatively decoupling the first connection interface and the second connection interface in response to disconnection of power to the relay during a bypass mode.

System and methods for an Advance Centralized Chronos Network on Chip (ACC-NoC) design are disclosed. The ACC-NoC is able to efficiently satisfy interconnect traffic requirements of modern Systems of Chip and simplify top level timing closure while providing high throughput and low latency. The ACC-NoC in a System on Chip may include a centralized intelligent switch and arbitration engine communicatively coupled to different intellectual property (IP) blocks through series of one or more Chronos Channels which transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic.

A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Provided are USB connector-free device and method, the device comprising: a host computer 10; a mobile device 20; and an ultra-high-speed module 30, wherein the host computer 10 comprises a USB module, the mobile device (20) comprises: a mobile device USB module (21) connected to the USB module of the host computer (10); mobile device hardware (22) matching with a hardware layer of the mobile device USB module (21); and a mobile device RF module (23) wirelessly matching with the mobile device hardware (22), and the ultra-high-speed module (30) comprises: an ultra-high-speed RF module (31) wirelessly communicating with the mobile device RF module (23); ultra-high-speed module hardware (32) matching with the ultra-high-speed RF module (31) by hardware; and a memory module (33) performing wire-communication with the ultra-high-speed module hardware (32).

Systems and methods for provisioning remote display of video streams. For instance, the system includes video cameras, monitoring devices and provisioning server(s). Each video monitoring device includes a client device and a display. The provisioning server is configured to: discover the video cameras by receiving discovery requests; register the video cameras, the registering including storing real time streaming protocol (RTSP) information in the provisioning database; discover the video monitoring devices by receiving discovery requests; register the video monitoring devices, the registering including storing display capabilities in the provisioning database; provide a provisioning portal, the provisioning portal including a graphical user interface for receiving provisioning instructions including assignments of the video cameras to the video monitoring devices, where the provisioning portal stores the received provisioning instructions in the provisioning database; and reconfigure, responsive to the received provisioning instructions, the video monitoring devices to display outputs of selected cameras on the display.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.