Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

A system for data transmission between two devices, including an output device having a binary output interface and a first field device having a binary input interface connected in a signal-transmitting manner to the binary output interface via a unidirectional connection. The output device includes a signal processing module which is set up to convert a data set to be transmitted to a binary, discrete-time signal in accordance with a serial protocol. The first field device includes a signal processing module which is set up to convert the received binary, discrete-time signal to the data set in accordance with the serial protocol. The invention further relates to a valve system.

Systems and method are provided. An illustrative system includes a first compute node having a first processing unit, a first compute node port, and a first peripheral component interconnect bus configured to carry data between the first processing unit and the first compute node port. The system may further include a multi-host network interface controller having a first multi-host port, where the first multi-host port is configured to connect with the first compute node port via a first peripheral component interconnect cable, a network port, where the network port is configured to receive a network interface of a networking cable, and processing circuitry configured to translate and carry data between the first multi-host port and the network port.

An electronic device capable of accessing a memory card is provided. The electronic device includes a circuit board, a processing unit, a memory card slot, and a memory card access module. The processing unit is disposed on the circuit board. The memory card slot is disposed on the circuit board, allows the insertion of the memory card, and is coupled to the processing unit through a first signal line. The memory card access module is disposed on the circuit board for accessing the memory card. The memory card access module is coupled to the processing unit through a second signal line and coupled to the memory card slot through a third signal line and a fourth signal line. The first signal line, the second signal line, and the third signal line conform to the standard of a signal transmission interface.

A method of pairing a mobile computing device with an external device during set up of the mobile computing device, the method comprising, at a computing device initiate a setup application for the mobile computing device; determining if the mobile computing device has an internal scanner; when the mobile computing device does not have an internal scanner: prepare the mobile computing device for pairing with a peripheral scanning device; prepare the peripheral scanning device for pairing with the mobile computing device; pairing the mobile computing device with the peripheral scanning device; and scanning staging indicia with the peripheral scanning device to initiate a device staging application within the mobile computing device.

A plug for communication signal conversion, the plug including a first connector for synchronous communication signals, a second connector for Ethernet communication signals, and a converter for synchronous to Ethernet communication signal conversion, connected at a first end to the first connector and at a second end to the second connector, wherein the first connector, the second connector and the converter are included within a plug housing, and the plug housing is sized and shaped for plugging into a connector receptacle for communications signals. Related apparatus and methods are also described.

A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.