In accordance with one disclosed method, a client device may be caused to present a user interface for an application, the user interface enabling selective access to a plurality of resources via the client device. A state of a peripheral device that is connectable to the client device may be determined and, based at least in part on the state of the peripheral device, at least a first resource, from among the plurality of resources, may be identified with which the peripheral device can interact. Based at least in part on the identifying of the first resource, the user interface may be caused to include at least a first selectable user interface element that, when selected, causes the client device to access to the first resource so as to enable the peripheral device to interact with the first resource.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A method and apparatus for operating a smart network interface card are provided. According to an embodiment, the smart network interface card is connected to a baseboard management controller. The method includes: acquiring a smart network interface card detection request, the smart network interface card detection request includes an identifier of a to-be-detected smart network interface card; determining a baseboard management controller that is connected to the to-be-detected smart network interface card as a target baseboard management controller; and logging into an operating system of the to-be-detected smart network interface card through the target baseboard management controller. This embodiment provides a new approach of operating the smart network interface card.

The present disclosure provides a method and a system for automatically configuring an I/O port. The method applied to a central processor includes: receiving request information from a controlled device, the request information carrying a type of a signal required by the controlled device, and sending, according to the type of the signal, a configuration instruction to a control device, and instructing the control device to configure the I/O port according to the configuration instruction. The controlled device is connected to the central processing unit, or the controlled device is connected to the central processor by means of the control device.

A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

A smart network interface card (SNIC) is provided. The SNIC may connect to an interconnect module (ICM) having at least two internal data paths. The SNIC and ICM determine a division of work between them. In general, NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some SNICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality. Packets received from devices providing a division of work (e.g., SNICs) may receive reduced processing for functions offloaded to the SNIC. SNICs may utilize either a switching and routing group or a virtual bypass group such that data may bypass selected processing typically performed by the ICM.

In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.