Patent classifications
G06F13/387
Virtualized link states of multiple protocol layer package interconnects
Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
Joint electron devices engineering council (JESD)204-to-peripheral component interconnect express (PCIe) interface
A system and method are provided for interfacing JESD204-to-PCIe communications. The method transceives JESD204 link layer messages with a JESD204 link layer. The method converts between JESD204 link layer messages and PCIe scrambled messages. The method converts between PCIe scrambled messages and PCIe encoded messages. The PCIe encoded messages are transceived at a JESD clock rate. The PCIe encoded messages transceived at the JESD clock rate are buffered and PCIe encoded messages are then transceived at a PCIe clock rate. The PCIe encoded messages at the PCIe clock rate are transceived with a PCIe physical layer. That is, PCIe encoded messages are either transmitted to the PCIe physical layer at the PCIe clock rate (the transmission path), or received from the PCIe physical layer (at the PCIe clock rate) and buffered (the receive path). The system and method also enable conventional JESD link layer-to-JESD physical layer communications.
PROCESSING OF PROCESS DATA
A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.
METHODS, DEVICES, AND SYSTEMS FOR TIMING AND BANDWIDTH MANAGEMENT OF ULTRA-WIDEBAND, WIRELESS COMMUNICATION CHANNELS
Disclosed herein are methods, devices, and systems for providing timing and bandwidth management of ultra-wideband, wireless data channels (including radio frequency and wireless optical data channels). According to one embodiment, a hub apparatus is disclosed for providing out-of-band bandwidth management for a free-space-optical (FSO) data channel associated with a first device. The hub apparatus includes a processor, a memory coupled with the processor, an FSO transmitter coupled with the processor, and an FSO receiver coupled with the processor. The FSO transmitter may be configured to transmit a control signal comprising timing information and bandwidth management information.
SEMICONDUCTOR DEVICE AND METHOD FOR PROTECTING BUS
The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
SYSTEM INCLUDING PIPE5 TO PIPE4 CONVERTER AND METHOD THEREOF
Embodiments of the present invention provide a PIPE5 to PIPE4 converter to provide compatibility between a PIPE5 controller and a PIPE4 test device. The converter includes a first interface coupled to the PIPE5 controller including MAC registers through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and PHY registers. When a first message bus interface signal is received from the PIPE5 controller, the first interface finds a target PHY register based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device.
DATA TRANSMISSION METHOD AND DATA TRANSMISSION SYSTEM
A data transmission method, applied to a data transmission system comprising a reception interface and a plurality of transmission interfaces, comprising: (a) receiving first transmission information from a source device via the reception interface, wherein the first transmission information comprises information of data groups corresponding to at least two of the transmission interfaces; and (b) transmitting at least portion of the data groups by a corresponding one of the transmission interfaces in turn to a target device which corresponds to the data group comprising the portion, according to the first transmission information, until transmission of all of the data groups is completed.
DEVICE AND METHOD FOR ALLOWING INTEGRATION OF INCOMPATIBLE DEVICES INTO A VEHICLE BUS NETWORK
A device and method for communication among vehicle components operating on different electronic vehicle bus communication protocols is disclosed. The current invention is specifically designed with the capabilities and reliability required for permanent integration of an incompatible device into a vehicle bus network. This allows for installation and permanent integration of incompatible devices onto new and advanced vehicles which are manufactured using the latest electronic vehicle bus communication protocols.
A DEVICE CAPABLE OF BEING OPERATED IN DIFFERENT MODES
A computing device may have a number of ports that can be connected to different peripheral devices and the availability, capability and/or functionality available through different ports may change depending on a mode of operation of the computing device. A user will not generally be aware of which ports can be used as they are all, in theory, available and the usability of an individual port is likely to change if a different host device is connected to the docking station or according to the mode the computing device is operating in. This is especially the case if the ports can all accept the same plug, for example, a USB Type-C plug. In order to allow a user to see easily which port is/are active to provide a particular capability, a controller determines a mode of operation of the device, the mode of operation being such that particular capabilities are made available at one or more of the plurality of peripheral ports, and controls an indicator associated with a particular peripheral port to provide an indication that the particular peripheral port is active to provide a capability if a peripheral device requiring that capability is connected to the particular peripheral port.
AUTO ADDRESSING USING FUNCTIONAL CONNECTION
An apparatus for auto addressing includes a communication bus interface configured to receive an address assignment request to assign an address to the apparatus. A functional connection is configured to activate a device connected to the apparatus. A detector is configured to measure a characteristic of the device and to compare the characteristic with a validation parameter. The characteristic depends on the functional connection. An address assignment circuit is configured to store the address in a memory of the apparatus in response to receiving the address assignment request at the apparatus, and the characteristic being validated with the validation parameter.