G06F13/387

SYSTEMS AND METHODS FOR FLEXIBLE HDD/SSD STORAGE SUPPORT
20170322898 · 2017-11-09 ·

Various examples of the present technology provide systems and methods for incorporating a switch card and adapter cards in a server system to provide flexible HDD and SSD supports. More specifically, a server system comprises a switch card having at least two different types of interfaces (e.g., a Serial Attached SCSI (SAS) interface, a serial ATA (SATA) interface, or a Peripheral Component Interconnect Express (PCIe) interface), and a controller that comprises a first Central Processing Unit (CPU) and a second CPU. The first CPU is connected to a first adapter card while the second CPU is connected to a second adapter card. The first adapter and the second adapter are coupled to the switch card of the server system.

Method of communication between multiple devices using USB type-C interface and electronic device implementing same
11249936 · 2022-02-15 · ·

A method and electronic device for communicating multi devices that use universal serial bus (USB) type-C are provided. The electronic device includes at least one or more interfaces formed as USB type-C, and at least one control circuit electrically connected to the interface. The control circuit may be configured to form a communication path, through chosen terminals of the interfaces, between at least two or more external devices connected to the interfaces.

Low power parallelization to multiple output bus widths

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Network input/output structure of electronic device
11249930 · 2022-02-15 · ·

A network input/output structure of an electronic device includes a FPGA module, a multiple of UART voltage conversion transceivers, at least one network connector and at least one detection module. Each UART voltage conversion transceiver has an input/output pin definition of a brand specification of a network device. The FPGA module uses the detection module to detect the pin definition of an external network device to confirm the brand specification of the network device and turn on a voltage conversion chip of the UART voltage conversion transceiver of the brand specification, so that the external network device can transmit network information with the electronic device automatically.

EMPLOYING SESSION LEVEL RESTRICTIONS TO LIMIT ACCESS TO A REDIRECTED INTERFACE OF A COMPOSITE DEVICE
20170264649 · 2017-09-14 ·

Session level restrictions can be implemented to limit access to a redirected interface of a composite device. These session level restrictions can be defined within a policy of a directory service, such as Active Directory, to facilitate the dynamic application of the restrictions to the appropriate remote sessions. In this way, access restrictions can be applied to individual interfaces of a redirected composite device so that a particular interface will only be accessible from specified remote sessions.

USB device and method for processing data by USB device
09760519 · 2017-09-12 · ·

A universal serial bus device receives a data packet from a host. The universal serial bus device includes a first virtual device, a second virtual device and a data-assigning device. The data-assigning device performs a determination operation, including: transmitting data corresponding to the a first logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the first logical address and the first logical address are recorded in the data packet; transmitting data corresponding to the a second logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the second logical address and the second logical address are recorded in the data packet.

SECURITY COMPONENT FOR DEVICES ON AN ENUMERATED BUS
20210397750 · 2021-12-23 · ·

A plug-and-play (PnP) driver associated with a security agent is described herein. The PnP driver attaches to device stacks of enumerated bus devices of a computing device as upper-device or lower-device filters based on the device classes of the enumerated bus devices. For example, the PnP driver may attach to the device stack of a hub or controller device as an upper-device filter and to device stacks of other devices as lower-device filters. Either while attaching or after attachment, the PnP driver may take action to alter, limit, or otherwise block functionality of an enumerated bus device. The PnP driver may also perform a system inventory of enumerated bus devices connected to the computing device and create fingerprints for one or more of the computing devices. Additionally, the PnP driver may create and remove control device objects (CDOs) to enable communication with user-mode processes or threads.

SYSTEMS AND METHODS OF PROVIDING AN ABSTRACTION LAYER BETWEEN AN APPLICATION LAYER AND HARDWARE COMPONENTS OF A COMPUTING DEVICE

A method of providing an abstraction layer between an application layer and one or more existing hardware components of a computing device includes receiving a request for a resource from the application layer, determining a component type for performing a task according to the request for the resource, determining whether the one or more existing hardware components of the computing device correspond to the component type for performing the task based on a predetermined function of the one or more existing hardware components, converting the task into a translated task readable by the one or more existing hardware components, providing the translated task to the one or more existing hardware components, receiving an output from the one or more existing hardware components as a result of providing the translated task, and providing the output to the application layer as an emulated output that mimics an expected output of the component type.

ELECTRONIC DEVICE, INFORMATION PROCESSING SYSTEM AND METHOD
20210390073 · 2021-12-16 · ·

According to one embodiment, in a first state, a control circuit determines, based on first information and second information, information on a request that includes a setting of a transmission circuit of a host to be set as an initial setting in a second state. The first state is a state of communicating with a host at a first communication speed conforming to a first specification. The second state is a state of communicating with the host at a second communication speed conforming to a second specification. The second communication speed is different from the first communication speed. The first information is information on a request of a setting of the transmission circuit of the host. The second information is information on a quality of a signal received by a reception circuit, which has been transmitted from the transmission circuit of the host.

MULTI-CHIP SYSTEM AND DATA TRANSMISSION METHOD THEREOF

A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.