In accordance with some aspects of the present disclosure, a non-transitory computer readable medium is disclosed. In some embodiments, the non-transitory computer readable medium includes instructions that, when executed by a processor, cause the processor to receive, from a workload hosted on a host of a cluster, first I/O traffic programmed according to a first I/O traffic protocol supported by a cluster-wide storage fabric exposed to the workload as being hosted on the same host. In some embodiments, the workload is recovered by a hypervisor hosted on the same host. In some embodiments, the non-transitory computer readable medium includes the instructions that, when executed by the processor, cause the processor to adapt the first I/O traffic to generate second I/O traffic programmed according to a second I/O traffic protocol supported by a repository external to the storage fabric and forward the second I/O traffic to the repository.

Systems and methods enable data collection and analytics consumption with a generalized assurance framework using a message bus that supports a publish-subscribe model. A producer network element subscribes to a request topic on the message bus and posts, to the message bus, an announcement indicating a data topic is available from the producer network element. The producer network element receives via the message bus, the request topic including a request for the data topic and posts, to the message bus, records for the data topic in response to the request.

A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

A low pin count (LPC) bus serial interrupt system includes: an interrupt direction signal generator configured to determine a current interrupt direction signal according to whether a host currently sends a first interrupt signal to an external device; and a level-shifter configured to convert a voltage level of a signal exchanged between the host and the external device according to the current interrupt direction signal.

The present disclosure provides a storage system including a first storage device (e.g., a main storage device) and one or more additional storage devices (e.g., sub storage devices). The first storage device includes a host interface for communicating with a host device and is directly connected to the host device. The additional storage devices may be directly connected to the first storage device and may communicate with the host device through the host interface included in the first storage device. The storage system thus has a total combined capacity of both the capacity of the first storage device and the capacity of the one or more additional storage devices. Further, the one or more additional storage devices may be added or removed to increase or decrease the total capacity of the storage system, and the one or more additional storage devices may not necessarily themselves include a host interface.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Each device on a bus auto-enumerates at power up or reset to assign a unique address to the device based on the resistance value of an external resistor. A current source supplies a current to a terminal to which a resistor is coupled. Each device has a resistor attached with a different resistance value. Each device senses the voltage at the terminal and the voltage corresponds to the unique device address on the bus. Following enumeration, the devices on the bus are individually addressable using their unique address.

A compact expansion card riser assembly for connection of two expansion cards to horizontally oriented circuit board is disclosed. The riser assembly includes a support bracket, a first horizontal riser board, and a second horizontal riser board. The first horizontal riser board has an expansion card connector. The first horizontal riser is attached to the support bracket. The support bracket and first horizontal riser board support a horizontally oriented expansion card. The second horizontal riser board has an expansion card connector. The second horizontal riser is attached to the support bracket. The support bracket and second horizontal riser board support a horizontally oriented expansion card.

Circuit including a first port to couple to a first device; a second port to couple to a second device; a first channel having an input coupled to first port and an output coupled to second port, the first channel to re-drive a signal and output re-driven signal; a second channel having an input coupled to second port and an output coupled to first port, the second channel to re-drive a signal and output re-driven signal; and a controller to: enable first channel and disable second channel responsive to detecting a signal edge at first port; enable second channel and disable first channel responsive to detecting a signal edge at second port; sample impedance at first port if signal received at first port is de-asserted while first channel is enabled; and sample impedance at second port if signal received at second port is de-asserted while second channel is enabled.