The present invention provides a SoC including a first CPU, a first tightly-coupled memory, a second CPU and a second tightly-coupled memory is disclosed. The first CPU includes a first core circuit, a first level one memory interface and a first level two memory interface. The first tightly-coupled memory is directly coupled to the first level one memory interface, and the first tightly-coupled memory includes a first mailbox. The second CPU includes a second core circuit, a second level one memory interface and a second level two memory interface. The second tightly-coupled memory is directly coupled to the second level one memory interface, and the second tightly-coupled memory includes a second mailbox. When the first CPU sends a command to the second mailbox within the second tightly-coupled memory, the second core circuit directly reads the command from the second mailbox, without going through the second level two memory interface.

Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element can include a plurality of interconnects to receive a plurality of inputs corresponding to the multiple busses. Each processing element of a given columnar bus can receive an input from a prior element of the given columnar bus at an active bus position and perform arithmetic operations on the input. Each processing element can further receive a plurality of inputs at passive bus positions and provide the plurality of inputs to subsequent processing elements without the plurality of inputs being processed by the processing element. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

A compact expansion card riser assembly for connection of two expansion cards to horizontally oriented circuit board is disclosed. The riser assembly includes a support bracket, a first horizontal riser board, and a second horizontal riser board. The first horizontal riser board has an expansion card connector. The first horizontal riser is attached to the support bracket. The support bracket and first horizontal riser board support a horizontally oriented expansion card. The second horizontal riser board has an expansion card connector. The second horizontal riser is attached to the support bracket. The support bracket and second horizontal riser board support a horizontally oriented expansion card.

A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Systems and methods enable data collection and analytics consumption with a generalized assurance framework using a message bus that supports a publish-subscribe model. A producer network element subscribes to a request topic on the message bus and posts, to the message bus, an announcement indicating a data topic is available from the producer network element. The producer network element receives via the message bus, the request topic including a request for the data topic and posts, to the message bus, records for the data topic in response to the request.

A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

A multi-port data storage device to at least provide port-to-port communication between nodes. The multi-port storage device includes a first port, a second port and a bridge. The first port can be operatively coupled to a first node of a plurality of nodes. The second port can be operatively coupled to a second node of the plurality of nodes. The bridge can receive one or more data packets via the first or second ports to be transmitted to one of the plurality of nodes and to transmit one or more received data packets to another multi-port data storage device, to the first node, or to the second node.

Reconfigurable interconnection nodes and interface modules are provided. The reconfigurable interconnection node includes a circuit board with a processing unit executing instructions stored on memory to provide operating system software, at least one bus, and at least one bus connector. The reprogrammable interconnection node also includes at least one system interface module operably connected to the circuit board via the at least one bus, wherein the system interface module is configured to communicate with or exchange data with at least a first external system.

A method is performed by a bus coupler of a subnetwork of one or more local subnetworks coupled to an overall network is provided, including performing a local discovery process for discovering and identifying one or more bus devices included in the subnetwork. The method further includes submitting an internet protocol (IP) address request to obtain an IP address for the bus coupler, receiving at the bus coupler the IP address of the bus coupler in response to the IP address assignment request, submitting a configuration request for configuration information associated with a device name for the bus coupler, receiving the configuration information in response to the configuration request, and configuring at least one feature of the bus coupler using the configuration information, wherein the device name is based on identifier(s) of the respective one or more bus devices obtained by the discovery process.