A system includes a processor configured to detect a vehicle key and display a key identification on a vehicle display. The processor is also configured to receive a request to export vehicle system and state settings to a key memory. The processor is further configured to access a plurality of predefined settings, designated as key-storable settings, from a vehicle CAN bus, responsive to the request, and transmit the predefined settings to the key, including instructions to store the settings to the key memory.

A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.

Techniques are disclosed for managing the connection assignments of a plurality of accessory devices to one or more hub devices. In one example, a user device acting as a leader device receives an assignment request from an accessory device. The user device may obtain information corresponding to hub attributes from the one or more hub devices. The user device may also obtain accessory traits from the accessory device. The user device can compare the accessory traits with the hub attributes to determine a connection score for each hub device. The user device can then assign the accessory device to the hub device with the highest connection score.

Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.

The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.

In an example of the described techniques, a wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.

An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Methods, systems, and apparatuses, including computer storage media and hardware security modules, for performing batch cryptography on hardware security modules. A hardware security module can receive a request to perform one or more cryptographic operations. The request can include a batch data structure storing a plurality of data elements. The hardware security module can unbatch the plurality of data elements, perform one or more cryptographic operations on the plurality of data elements to generate a plurality of outputs, generate an output batch data structure storing the plurality of outputs, and transmit the output batch data structure in response to the request. The request and the batch data structure can be formed in accordance with a batch hardware security module application program interface (API) implemented by the hardware security module.

A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

Techniques are described for reconciling events timestamped in different time domains in multi-node systems supporting low-latency hardware timestamping. First and second nodes having independent time bases are synchronized by the first node generating an event that is received effectively simultaneously at the first and second nodes, the first and second nodes recording a timestamp of receipt of the event, the first node asynchronously querying the second node for its timestamp of receipt of the event and comparing its timestamp of receipt of the event with the timestamp of receipt of the event by the second node, and the first node using a difference in the timestamps of receipt of the event by the first and second nodes to align the time bases of the first and second nodes. The nodes may include hardware timestamping functionality or use an external component (e.g., field programmable gate array) to provide the timestamping functionality.