A remote terminal adapter device is disclosed. The adapter device includes control processors in communication with a bus controller via a dual redundant data bus (e.g., MIL-STD-1553) having primary and secondary data buses or channels. The adapter device includes analog relays connecting the primary and secondary buses to a main remote terminal (RT) device configured for control of an aircraft subsystem. Additional analog relays connect the data bus to one or more auxiliary or additional RTs (e.g., configured to backup the main RT or simulate the controlled subsystem and its responses. The adapter device may monitor the data bus for traffic and allow the redundant RT to access the data bus (from the same remote terminal) address as the main RT by activating and deactivating the analog relays.

An endoscope motherboard, an endoscope and a detection method are provided. The endoscope motherboard is connected to a terminal and a camera module. The endoscope motherboard includes a communication interface, a wireless communication module and an adapter board. The communication interface and the wireless communication module are connected to the adapter board. The adapter board is connected to the camera module. The communication interface or the wireless communication module is connected to the terminal. The adapter board includes a detection module and a gating switch. The detection module detects a status of connection between the communication interface or the wireless communication module and the terminal and transmit a signal to the gating switch according to the status of connection. The gating switch connects the camera module to the communication interface or the wireless communication module according to the signal.

An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

In an example of the described techniques, a wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.

In some examples, an adapter device includes a bridge to determine that a storage device includes a plurality of bus controllers, where the plurality of bus controllers are communicatively coupled to respective adapter devices. The bridge determines a quantity of supported connections over the network to the storage device, and in response to determining that the storage device comprises the plurality of bus controllers, the bridge computes an identifier based on the quantity of supported connections and to which respective bus controller of the plurality of bus controllers the adapter device is connected, and assigns the identifier to a connection from the host to the storage device.

A system and a method of interface communication being compatible with SFP+ optical modules and QSFP+ switch are provided. The system includes an adapter card. The adapter card includes a set of SFP+ golden fingers that comply with the SFP+ protocol, a set of QSFP+ golden fingers that comply with the QSFP+ protocol, and a microcontroller unit. The adapter card communicates with the SFP optical module through the SFP+ golden fingers, and communicates with the QSFP switch through the QSFP+ golden fingers. The microcontroller unit is used to extend and process the pin information in the adapter card, and to convert the two different protocols of SFP+ and QSFP+, so that the module under the SFP+ protocol can respond under the port of QSFP+, so as to realize the data communication between the SFP+ optical module and the QSFP+ switch.

Examples of the disclosure include a host system comprising an authentication communication medium interface configured to be communicatively coupled to a connected module, a secure communication medium interface, and a controller configured to detect a connection of the connected module to the host system over a physical communication connection, generate an authentication challenge, provide the authentication challenge to the connected module over a physical authentication connection via the authentication communication medium interface, receive a challenge response to the authentication challenge from the connected module via the authentication communication medium interface, verify the challenge response, and grant the connected module access to host system data over the physical communication connection via the secure communication medium interface based on successful verification of the challenge response.

An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Disclosed are a method and a Universal Flash Storage (UFS) system for performing save state switching using selective lanes between a first electronic device and a second electronic device. The method includes: determining, by the first electronic device, whether a data request is received from an application layer of the first electronic device; and performing, by the first electronic device, at least one of: setting a first lane from among a plurality of lanes between the first electronic device and the second electronic device to an active state and the other lanes from among the plurality of lanes to a power save state based on determining that the data request is not received from the application layer of the first electronic device; and setting the plurality of lanes between the first electronic device and the second electronic device to the active state based on determining that the data request is received from the application layer of the first electronic device.

Method for controlling commands suitable to be processed by a peripheral (2) comprising the following steps implemented by a control circuit (6) connected to a communication bus (8), a command circuit (4) and the peripheral (3) also being connected to the communication bus (8): granting or refusing authorization to the command circuit (4) to transmit a command signal of the peripheral via the bus (8), detecting the possible transmission of the command signal for the peripheral by the command circuit via the bus (8), implementing protection measures (614) when the control circuit detects that the command signal has been transmitted as the control circuit has not granted authorization, or that the command signal has not been transmitted as the control circuit has granted authorization.