Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.

A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor.

A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

Techniques for transmitting data include one or more processors of a computing device included in a network device identifying data to be transmitted, wherein the computing device includes the one or more processors, a queue, and a transmitter, and wherein the network device includes the computing device and a transceiver that is configured to transmit data outside of the network device; adding the data to the queue; and during an open data session window: transmitting, via the transmitter and to the transceiver, data extracted from the queue; and in response to determining that an amount of data in the queue is below a threshold, (a) delaying for a period of time, and (b) after the period of time, instructing the transceiver to end the open data session window early and transition to a lower power state.

A link balance adjustment method includes the following steps. A connection port initiates a balance adjustment process through an interrupt signal. A microprocessor provides an adjustment parameter for an external device from a register and transmits the adjustment parameter to the connection port. A measurement signal is initiated by the microprocessor, and the measurement signal enables the connection port to measure the signal quality after the adjustment parameter has been applied by the external device. The microprocessor determines whether the connection port needs to perform a preprocessing. When the microprocessor determines that the connection port needs to perform a preprocessing, the connection port performs the preprocessing and generates preprocessing data. The connection port transmits the preprocessing data to the register. The microprocessor reads the preprocessing data or the signal quality in the register.

An information handling system includes multiple data ports, a memory, and a processor. Each of the data ports enables a separate communication link of a plurality of communication links for the information handling system. The memory stores data to indicate whether the information handling system supports bridge assurance on each of the communication links. In response to the bridge assurance being supported in the information handling system, the processor provides a message across a first link of the communication links. The message indicates that bridge assurance is supported in the information handling system. The processor also determines whether an acknowledgement message has been received. In response to the acknowledgement message being received, the processor enables the bridge assurance on the first link.

A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.

A system includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests.

Disclosed by the present application are a method, master device and system for data communication. The method comprises: initiating a communication signal to an interface in an interface module; when response information from a slave device connected in the interface is received, adding physical ID information of the interface into an online queue, wherein the probability that interfaces in the online queue is subsequently initiated by the communication signal is higher than that of interfaces in an idle queue; and receiving data information transmitted by the slave device in the interface. The data communication master device of the present application comprises a communication signal initiation unit, an online interface identification unit and a data information receiving unit corresponding to the implementation of steps of the described method. Therefore, the communication network for multiple slave devices and a master device has high communication efficiency.

Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.