Systems, methods, and/or apparatuses may be operative to perform a dialysis process that includes a displacer infusion process. The dialysis machine may include at least one processor and a memory coupled to the at least one processor, the memory comprising instructions that, when executed by the processor, may cause the at least one processor to access dialysis information for a dialysis process performed by a dialysis machine, the dialysis information indicating a target substance to be displaced from a binding compound by a displacer, and determine an infusion profile for infusing the displacer into a patient during a displacer infusion process of the dialysis process, the infusion profile determined based on the dialysis information and an infusion constraint. Other embodiments are described.

Systems, methods, and/or apparatuses may be operative to perform a dialysis process that includes a displacer infusion process. The dialysis machine may include at least one processor and a memory coupled to the at least one processor, the memory comprising instructions that, when executed by the processor, may cause the at least one processor to access dialysis information for a dialysis process performed by a dialysis machine, the dialysis information indicating a target substance to be displaced from a binding compound by a displacer, and determine an infusion profile for infusing the displacer into a patient during a displacer infusion process of the dialysis process, the infusion profile determined based on the dialysis information and an infusion constraint. Other embodiments are described.

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. A first tile in a first node can include a processor with a processor output and a first register network configured to receive information from the processor output and information from one or more of the multiple other tiles in the first node. In response to an output instruction and a delay instruction, the register network can provide an output signal to one of the multiple other tiles in the first node. Based on the output instruction, the output signal can include one or the other of the information from the processor output and the information from one or more of the multiple other tiles in the first node. A timing characteristic of the output signal can depend on the delay instruction.

Methods, systems, and devices for access control configurations for inter-processor communications are described to support reconfiguration of a dynamic access control configuration at a device. For example, additional configuration fields may be added to existing access control rules of the device, where these additional fields may be configured by a processor sending information to a receiving processor, via a shared memory resource or region of the device. The additional fields may include a read-only value which may specify a processor which has exclusive write permission for a memory region of the share memory. This value may indicate the sending processor of the memory region, and the value may be set by access control hardware when the additional field is changed. Other processors of the device may be prevented from writing to the memory region.

Controller devices may be configured to execute a network discovery service to identify other devices on a network, including other controller devices, user computing devices, and/or human machine interface devices. The controller devices may communicate with the devices on the network. An individual controller device may, upon connection to a human machine interface device, provide to the human machine interface device via a web server, a graphical user interface from which a user may configure the controller device or connect to another controller device on the network.

An improved system and method are disclosed for improving functionality in software applications. In one example, the method includes a computing entity having a network interface, a processor, and a memory configured to store a plurality of instructions. The instructions include instructions for a superblock application having instructions for a function block included therein. The function block is configured to provide functions that are accessible to the superblock application via an application programming interface (API). The functions are provided within the superblock application itself and are accessible within the superblock application without switching context to another application on the computing entity.

An improved system and method are disclosed for improving functionality in software applications. In one example, the method includes a computing entity having a network interface, a processor, and a memory configured to store a plurality of instructions. The instructions include instructions for a superblock application having instructions for a function block included therein. The function block is configured to provide functions that are accessible to the superblock application via an application programming interface (API). The functions are provided within the superblock application itself and are accessible within the superblock application without switching context to another application on the computing entity.

The subject matter described herein includes methods, systems, and computer readable media for improving remote direct memory access (RDMA) performance. A method for improving RDMA performance occurs at an RDMA node utilizing a user space and a kernel space for executing software. The method includes posting, by an application executing in the user space, an RDMA work request including a data element indicating a plurality of RDMA requests associated with the RDMA work request to be generated by software executing in the kernel space; and generating and sending, by the software executing in the kernel space, the plurality of RDMA requests to or via a system under test (SUT).