An interconnection system including a first gating unit and a second gating unit is provided. The first gating unit includes two terminals, with one terminal connecting to a first CPU directly, where the two terminals are indirectly connected when the first gating unit is in a first state. The second gating unit includes two terminals, with one terminal connecting to a second CPU, where the two terminals are connected when the second gating unit is in the first state. Another terminal of the first gating unit is connected to another terminal of the second gating unit. If both the first gating unit and the second gating unit are in the first state, the first CPU is connected to the second CPU.

Implementations of the present specification provide a method and an apparatus for extending question and answer samples. According to the method, a random number is generated for each existing sample, a question is blurred for a sample whose random number belongs to sample extension random numbers, to generate an extended sample, so that an overall sample blurring extension rate can be effectively controlled. In addition, for a sample needing blurring extension, a question is extended by deleting a word with a predetermined part of speech in the corresponding question, and then an extended sample is generated based on an extended question, so that more question expression ways are compatible. As such, a question and answer model is trained by using a sample set to which extended samples are added, so that an answer can be provided to a user more effectively.

A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

Provided is a communication system including: a first communication bus available for communication of at least a first communication scheme; a second communication bus available for both communication of the first communication scheme and communication of a second communication scheme having a lower processing load than the first communication scheme; a plurality of first communication devices connected to both the first communication bus and the second communication bus; a plurality of second communication devices, connected to the second communication bus, which perform communication through the second communication scheme using the second communication bus; and a processor that detects an abnormality of the first communication bus, wherein each of the plurality of first communication devices performs communication through the first communication scheme using the first communication bus in a case where the abnormality of the first communication bus is not detected by the processor, and performs communication through the first communication scheme using the second communication bus in a case where the abnormality of the first communication bus is detected by the processor.

Provided is a communication system including: a first communication bus available for communication of at least a first communication scheme; a second communication bus available for both communication of the first communication scheme and communication of a second communication scheme having a lower processing load than the first communication scheme; a plurality of first communication devices connected to both the first communication bus and the second communication bus; a plurality of second communication devices, connected to the second communication bus, which perform communication through the second communication scheme using the second communication bus; and a processor that detects an abnormality of the first communication bus, wherein each of the plurality of first communication devices performs communication through the first communication scheme using the first communication bus in a case where the abnormality of the first communication bus is not detected by the processor, and performs communication through the first communication scheme using the second communication bus in a case where the abnormality of the first communication bus is detected by the processor.

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

Disclosed are a system comprising a computer-readable storage medium storing at least one program, and a computer-implemented method for event messaging over a network. A subscription interface receives data indicative of a subscription request for sessionized data. An allocation module allocates a sessionizer bank linked to the subscription request. A messaging interface module provisions identifiers linked to the respective processing engines of the sessionizer bank. The messaging interface module registers the allocated sessionizer bank as available to process event messages matching the subscription request by providing the provisioned identifiers. The messaging interface module receives event messages from a producer device linked by a collection server to a selected one of the processing engines of the sessionizer bank. The selected one of the processing engine processes the received event messages in accordance with session rule data linked to the subscription request to generate sessionized data.

Disclosed are a system comprising a computer-readable storage medium storing at least one program, and a computer-implemented method for event messaging over a network. A subscription interface receives data indicative of a subscription request for sessionized data. An allocation module allocates a sessionizer bank linked to the subscription request. A messaging interface module provisions identifiers linked to the respective processing engines of the sessionizer bank. The messaging interface module registers the allocated sessionizer bank as available to process event messages matching the subscription request by providing the provisioned identifiers. The messaging interface module receives event messages from a producer device linked by a collection server to a selected one of the processing engines of the sessionizer bank. The selected one of the processing engine processes the received event messages in accordance with session rule data linked to the subscription request to generate sessionized data.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.