A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

A control system that distributes information from a control device to a reception device includes a read request transmission unit that transmits a read request for information to the control device, an information generation unit that generates information in response to the read request, an information transmission unit that transmits the generated information to the reception device, and a distribution cycle computation unit that computes a distribution cycle based on a generation interval of the read request. The information transmission unit transmits the information in accordance with the distribution cycle computed by the distribution cycle computation unit.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the modification of online and offline business operations and marketing communications based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, process the input data set to obtain transformed clickstream data, analyze the transformed clickstream data to identify an order in which each user of the plurality of users views a plurality of product offerings, determine an average order position that a specific product offering of the plurality of product offerings is viewed, and modify an offline or online marketing communication associated with the specific product offering based on the average order position of the specific product offering.

Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the modification of online and offline business operations and marketing communications based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, process the input data set to obtain transformed clickstream data, analyze the transformed clickstream data to identify an order in which each user of the plurality of users views a plurality of product offerings, determine an average order position that a specific product offering of the plurality of product offerings is viewed, and modify an offline or online marketing communication associated with the specific product offering based on the average order position of the specific product offering.

A system for controlling a subsystem of a vehicle includes a memory, a first processor, and a second processor. The first processor allocates a portion of the memory upon booting to perform operations to control the subsystem and generates an indication when an amount of memory used from the allocated portion of the memory is greater than or equal to a threshold. The first processor monitors times when the vehicle is turned on and off and determines a time period during which the vehicle remains turned off. After the vehicle is turned off, the first processor enters a power save mode. The memory and the second processor continue to receive power. During the time period, on receiving the indication, the second processor wakes up the first processor, which performs a reboot operation, reallocates the memory, and reenters the power save mode. The memory continues to receive power.

Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.