A method, non-transitory computer readable medium and storage controller computing device that retrieves an anchor record from a shared memory of a peer storage controller using a direct memory access (DMA) provider device. The anchor record includes an indication of a message first in first out (FIFO) memory region of the peer storage controller. A work request is obtained from a queue. The work request is inserted into the queue by a client application using an application programming interface (API). One of a plurality of types of the work request is determined. The DMA provider device is instructed based on the determined type of the work request and, when the determining indicates that the work request is a request to send a network message, use the message FIFO memory region of the peer storage controller computing device.

Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Various examples described herein provide for determining a first data input/output (I/O) type of a computing device module and a second data I/O type of an I/O switch module, where the computing device module and the I/O switch module are coupled through a backplane system that includes a retimer. In response to the first data I/O type matching the second data I/O type, a connection between the computing device module and the I/O switch module may be permitted or prevented via the retimer.

Various examples described herein provide for determining a first data input/output (I/O) type of a computing device module and a second data I/O type of an I/O switch module, where the computing device module and the I/O switch module are coupled through a backplane system that includes a retimer. In response to the first data I/O type matching the second data I/O type, a connection between the computing device module and the I/O switch module may be permitted or prevented via the retimer.

An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and are connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and are connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. The arithmetic processing unit includes a pull data turn-back bus that propagates the pull data read from the register file of the home calculator unit to the pull data bus.

A distributed big data device in a process plant includes an embedded big data appliance configured to locally stream and store, as big data, data that is generated, received, or observed by the device, and to perform one or more learning analyzes on at least a portion of the stored data. The embedded big data appliance generates or creates learned knowledge based on a result of the learning analysis, which the device may use to modify its operation to control a process in real-time in the process plant, and/or which the device may transmit to other devices in the process plant. The distributed big data device may be a field device, a controller, an input/output device, or other process plant device, and may utilize learned knowledge created by other devices when performing its learning analysis.

A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.