Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.

A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.

A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.

A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.

A communication system for inter-chip communication includes system processors that communicate with one another via data channels of a communication bus. A processor designated as a master processor assumes control of the transmission to the other processor designated as a slave processor. A data channel is operated in a separate physical communication bus for each data communication direction.

A communication system for inter-chip communication includes system processors that communicate with one another via data channels of a communication bus. A processor designated as a master processor assumes control of the transmission to the other processor designated as a slave processor. A data channel is operated in a separate physical communication bus for each data communication direction.

Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package.

This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die.

The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die.

Moreover, the memory interfaces include an interface conforming to TCI.

In addition, the memory interfaces further include an interface conforming to HBM.

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.