G06F15/17

Method and apparatus for reporting of measurement data
09992697 · 2018-06-05 · ·

An apparatus, method and computer program product are provided to collect measurement data that may be useful for coverage optimization without having to rely as extensively upon drive tests. In this regard, an apparatus, method and computer program product may be provided for collecting and reporting upon measurement data. Additionally, an apparatus, method and computer program product may be provided for directing the collection of the measurement data and for then receiving a report of the measurement data. A corresponding system for collecting measurement data may also be provided.

Disjoint array computer
09977762 · 2018-05-22 · ·

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Disjoint array computer
09977762 · 2018-05-22 · ·

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Technique of link state detection and wakeup in power state oblivious interface

System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Technique of link state detection and wakeup in power state oblivious interface

System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

ELECTRONIC DEVICE AND DATA TRANSFER METHOD THEREOF
20180121268 · 2018-05-03 ·

An electronic device includes a memory storing software including an application, an inter-process communication (IPC) module supporting communication between processes, a first communication driver, and a second communication driver, and a processor executing the software stored in the memory. The processor is configured to determine, using the IPC module whether a destination of the data is inside the electronic device or outside the electronic device, if a transmission of data is requested from the IPC module by the application, to transmit the data through the first communication driver if the destination of the data is inside the electronic device, and to transmit the data through the second communication driver if the destination of the data is outside the electronic device.

CIRCUIT ARCHITECTURE MAPPING SIGNALS TO FUNCTIONS FOR STATE MACHINE EXECUTION
20240378171 · 2024-11-14 ·

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

CIRCUIT ARCHITECTURE MAPPING SIGNALS TO FUNCTIONS FOR STATE MACHINE EXECUTION
20240378171 · 2024-11-14 ·

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

Edge server selection for enhanced services network
09923897 · 2018-03-20 · ·

An enhanced services network provides enhanced privacy and/or security over public networks to client subscribers of the service. Client devices access the enhanced services network over a public communications network (e.g., the Internet, cellular network, etc.) via a client-side edge server of the enhanced services network. The enhanced services network interfaces with client-requested network resources hosted by third-party server devices via a resource-side edge server. The particular client-side edge server and/or resource-side edge server that is utilized for a particular client session may be selected by the enhanced services network according to a rule set. The rule set may seek to achieve one or more target goals, such as: (1) limit discoverability of the enhanced services network, (2) minimize or reduce geographic/network distance between an edge server and a target computing device, and/or (3) establish connections that are more secure than the connections originally requested by the client.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, MAIN PROCESSOR CORE, PROGRAM, INFORMATION PROCESSING METHOD, AND SUB PROCESSOR CORE
20180074980 · 2018-03-15 ·

A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.