A method is provided in one example embodiment and includes detecting by a first network element at a first data center site a local connection of an endpoint identifier (EID), in which the EID was previously locally connected to a second network element at a second data center site and notifying a mapping server of the local connection of the EID to the first network element. The method further includes receiving from the mapping server identifying information for the second network element and communicating with the second network element using the identifying information to obtain service information for traffic associated with the EID. The method may also include applying a service identified by the service information to outgoing traffic from the EID as well as applying a service identified by the service information to incoming traffic for the EID.

An electronic device and a power control method of an electronic device are provided. The electronic device may include: a communication circuit including a first circuit configured to perform first communication and a second circuit configured to perform second communication; a processor electrically connected to the communication circuit; and a memory electrically connected to the processor, wherein, the memory stores instructions that, when executed, cause the processor to perform operations comprising: controlling the first circuit to operate according to a first power control mode associated with the first communication, and controlling the second circuit to operate according to a second power control mode associated with the second communication when the first communication and the second communication are concurrently performed through the first circuit and the second circuit; identifying a first sleep period during which the first circuit operates in a sleep mode according to the first power control mode, and a second sleep period during which the second circuit operates in the sleep mode according to the second power control mode; and controlling the communication circuit to operate in a deep sleep mode in which the communication circuit operates with power that is less than or equal to a predetermined power in a period where the first sleep period and the second sleep period coincide.

An electronic device and a power control method of an electronic device are provided. The electronic device may include: a communication circuit including a first circuit configured to perform first communication and a second circuit configured to perform second communication; a processor electrically connected to the communication circuit; and a memory electrically connected to the processor, wherein, the memory stores instructions that, when executed, cause the processor to perform operations comprising: controlling the first circuit to operate according to a first power control mode associated with the first communication, and controlling the second circuit to operate according to a second power control mode associated with the second communication when the first communication and the second communication are concurrently performed through the first circuit and the second circuit; identifying a first sleep period during which the first circuit operates in a sleep mode according to the first power control mode, and a second sleep period during which the second circuit operates in the sleep mode according to the second power control mode; and controlling the communication circuit to operate in a deep sleep mode in which the communication circuit operates with power that is less than or equal to a predetermined power in a period where the first sleep period and the second sleep period coincide.

Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. The intermediate hardware elements can also be configured to segregate/distribute signals/commands/message received from the root hardware element to a plurality of specified hardware elements and/or intermediate hardware elements.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

An example method for simultaneously supporting, on a single VIC adapter (i.e. on a single network interface), RDMA transport according to multiple RoCE versions is disclosed. The method includes providing the VIC adapter with an indication of a RoCE version used for a particular RDMA connection between two compute nodes identified by a certain QP identifier, and then automatically configuring Egress (EG) packet classifier and flow table of the VIC adapter to encapsulate outgoing RDMA commands and automatically configuring Ingress (IG) packet classifier and flow table of the VIC adapter to decapsulate incoming RoCE packets for that RDMA connection according to the indicated RoCE version. Automatic encapsulation and decapsulation according to any one of the multiple RoCE versions that may be used for a particular RDMA connection, i.e. on a per-QP basis, advantageously allows co-existence of routable (i.e. RoCEv2) and non-routable (i.e. RoCEv1) RDMA solutions on a single network interface.