Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the creation of new online and offline business methods based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, convert the input data set into data files having a common file format with each data file corresponding to a user of the plurality of users and comprising an identifier for the user and a plurality of Uniform Resource Locations (URLs) associated with online actions of the user, access online information relating to search terms and webpages, and determine one or more metrics of user behavior, including a verticals metric and a search terms metric.

Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. The intermediate hardware elements can also be configured to segregate/distribute signals/commands/message received from the root hardware element to a plurality of specified hardware elements and/or intermediate hardware elements.

An artificial intelligence (AI) switch chip includes a first AI interface, a first network interface, and a controller. The first AI interface is used by the AI switch chip to couple to a first AI chip in a first server. The first network interface is used by the AI switch chip to couple to a second server. The controller receives, through the first AI interface, data from the first AI chip, and then sends the data to the second server through the first network interface. By using the AI switch chip, when a server needs to send data in an AI chip to another server, an AI interface may be used to directly receive the data from the AI chip, and then the data is sent to the other server through one or more network interfaces coupled to the controller.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

A data transmission method, includes: receiving a data packet to be transmitted, the data packet to be transmitted including data to be transmitted and chip identification information; determining a target first peripheral component interconnect express (PCIE) physical layer port corresponding to the chip identification information from a plurality of first PCIE physical layer ports, the plurality of first PCIE physical layer ports and a plurality of chips being interconnected one to one; distributing the data packet to be transmitted to the target first PCIE physical layer port; and transmitting the data packet to be transmitted to a receiving chip through the target first PCIE physical layer port, the receiving chip being a chip interconnected with the target first PCIE physical layer port.

A multi-core processor and a related inter-core communication method are provided. The multi-core processor includes an inter-core communication module and a plurality of processor cores. The plurality of processor cores include N first processor cores. Each of the N first processor cores is configured to: execute a first task to generate operation information, where the operation information includes a completion identifier of the first task, and one or more of a processor core identifier of the first processor core, an inter-core synchronization mode, or association information of the first task; and send the operation information to the inter-core communication module. The inter-core communication module is configured to: determine M second processor cores from the plurality of processor cores based on N pieces of operation information, and separately send the completion identifier to the M second processor cores. Inter-core communication can be performed more efficiently and cost-effectively.

One aspect of the present invention is an information processing system including a computer installed in a computer base, a first transceiver connected to the computer, a second transceiver installed in a user base used by a user, a device connected to the second transceiver, a network configured to perform communication between a plurality of the first transceivers and the second transceiver, and a controller configured to control connection between one of the plurality of the first transceivers and the second transceiver, in which the controller is configured to control connection between one of the plurality of the first transceivers and the second transceiver via the network having a circuit switching function.

One aspect of the present invention is an information processing system including a computer installed in a computer base, a first transceiver connected to the computer, a second transceiver installed in a user base used by a user, a device connected to the second transceiver, a network configured to perform communication between a plurality of the first transceivers and the second transceiver, and a controller configured to control connection between one of the plurality of the first transceivers and the second transceiver, in which the controller is configured to control connection between one of the plurality of the first transceivers and the second transceiver via the network having a circuit switching function.

A computer comprising a plurality of interconnected processing nodes arranged in a configuration in which multiple layers of interconnected nodes are arranged along an axis, each layer comprising at least four processing nodes connected in a non-axial ring by at least respective intralayer link between each pair of neighbouring processing nodes, wherein each of the at least four processing nodes in each layer is connected to a respective corresponding node in one or more adjacent layer by a respective interlayer link, the computer being programmed to provide in the configuration two embedded one dimensional paths and to transmit data around each of the two embedded one dimensional paths, each embedded one dimensional path using all processing nodes of the computer in such a manner that the two embedded one dimensional paths operate simultaneously without sharing links.