The present disclosure relates to a device for observing and/or inspecting a material web, comprising a first camera unit for capturing first image data of the material web; a first computing unit, connected to the first camera unit, adapted to receive the first image data; and a second computing unit adapted to receive the first image data from the first computing unit. The first and the second computing units are connected via a first USB line. The first image data is transferred to the second computing unit via the first USB line. A first USB interface of the first computing unit and a second USB interface of the second computing unit are connected via the first USB line. Another aspect of the present disclosure relates to a device for processing a material web, comprising the material web and the device for observing and/or inspecting the material web.

The present disclosure relates to a device for observing and/or inspecting a material web, comprising a first camera unit for capturing first image data of the material web; a first computing unit, connected to the first camera unit, adapted to receive the first image data; and a second computing unit adapted to receive the first image data from the first computing unit. The first and the second computing units are connected via a first USB line. The first image data is transferred to the second computing unit via the first USB line. A first USB interface of the first computing unit and a second USB interface of the second computing unit are connected via the first USB line. Another aspect of the present disclosure relates to a device for processing a material web, comprising the material web and the device for observing and/or inspecting the material web.

A control system includes: a master station including a PLC executing user program; and a remote station including a communication memory to which a PLC device is assigned, a slave communication unit, and a unit to or from which one or more pieces of data is input or output, and being connected to the master station through a network. The PLC transmits, to the slave communication unit, assignment object designation information designating an object that is among unit data input or output to or from the unit and to which a PLC device is assigned, and an assignment rule. The slave communication unit assigns unit data that is among unit data input or output to or from the unit and is designated by the received assignment object designation information to the communication memory based on the received assignment rule.

A control system includes: a master station including a PLC executing user program; and a remote station including a communication memory to which a PLC device is assigned, a slave communication unit, and a unit to or from which one or more pieces of data is input or output, and being connected to the master station through a network. The PLC transmits, to the slave communication unit, assignment object designation information designating an object that is among unit data input or output to or from the unit and to which a PLC device is assigned, and an assignment rule. The slave communication unit assigns unit data that is among unit data input or output to or from the unit and is designated by the received assignment object designation information to the communication memory based on the received assignment rule.

Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D.sub.(a,1) to a first processing circuit; the first processing circuit processes the data D.sub.(a,1) to obtain data D.sub.(1,2), the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D.sub.(1,2) to a second processing circuit; the second processing circuit to an m.sup.th processing circuit separately process the received data; and the arbiter receives data D.sub.(m,a) sent by the m.sup.th processing circuit. The processor further comprises an (m+1).sup.th processing circuit. Each processing circuit in the first processing circuit to the (m+1).sup.th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.

Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.

In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.