A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

In one embodiment, a method includes establishing a connection between a hardware switch and a console port, connecting the console port to a first central processing unit (CPU) using the hardware switch, and receiving, from the console port, a first character stream. The method also includes detecting, by the hardware switch, a first special character within the first character stream. The method further includes connecting, by the hardware switch, the console port to a second CPU in response to detecting the first special character within the first character stream.

In one embodiment, a method includes establishing a connection between a hardware switch and a console port, connecting the console port to a first central processing unit (CPU) using the hardware switch, and receiving, from the console port, a first character stream. The method also includes detecting, by the hardware switch, a first special character within the first character stream. The method further includes connecting, by the hardware switch, the console port to a second CPU in response to detecting the first special character within the first character stream.

A computer includes first and second computer devices of a first class. Each computer device of the first class includes first and second external ports, at least one memory controller to attach to external memory, and routing logic to route data from the first external port to one of the memory controller and the second external port. The computer further includes first and second computer devices of a second class. The first computer device of the second class is connected to the first external ports via respective first and second links. The second computer device of the second class is connected to the second external ports via respective third and fourth links. The first and second computer devices of the second class include processing circuitry to execute a computer program and are connected to the first and second links, or third and fourth links, respectively to transmit and receive messages.

An inter-processor communication method, an electronic assembly, and an electronic device are provided. The electronic device at least includes a first core and a second core. A plurality of communication channels is defined between the first core and the second core. Each of the plurality of communication channels having a communication performance different from each other. The inter-processor communication method includes: acquiring to-be-transmitted data, the to-be-transmitted data is data transmitted between the first core and the second core; acquiring a corresponding communication channel corresponding to the to-be-transmitted data from the plurality of communication channels as a target communication channel; transmitting the to-be-transmitted data via the target communication channel.

An inter-processor communication method, an electronic assembly, and an electronic device are provided. The electronic device at least includes a first core and a second core. A plurality of communication channels is defined between the first core and the second core. Each of the plurality of communication channels having a communication performance different from each other. The inter-processor communication method includes: acquiring to-be-transmitted data, the to-be-transmitted data is data transmitted between the first core and the second core; acquiring a corresponding communication channel corresponding to the to-be-transmitted data from the plurality of communication channels as a target communication channel; transmitting the to-be-transmitted data via the target communication channel.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.