Disclosed are various embodiments for receiving, via a network, a request from a client to establish a network tunnel over the network. A credential is received from the client in order to establish the network tunnel. The client is authenticated based upon the credential. The client negotiates, via the network, to establish the network tunnel.

A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A method is provided in one example embodiment and includes detecting by a first network element at a first data center site a local connection of an endpoint identifier (“EID”), in which the EID was previously locally connected to a second network element at a second data center site and notifying a mapping server of the local connection of the EID to the first network element. The method further includes receiving from the mapping server identifying information for the second network element and communicating with the second network element using the identifying information to obtain service information for traffic associated with the EID. The method may also include applying a service identified by the service information to outgoing traffic from the EID as well as applying a service identified by the service information to incoming traffic for the EID.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, an input/output (I/O) latency value based on an I/O latency associated with each storage volume controlled by a respective storage controller. An I/O latency value threshold is determined. Responsive to a change to the I/O latency value exceeding a threshold, storage volume distribution among the storage controllers is rebalanced.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, an input/output (I/O) latency value based on an I/O latency associated with each storage volume controlled by a respective storage controller. An I/O latency value threshold is determined. Responsive to a change to the I/O latency value exceeding a threshold, storage volume distribution among the storage controllers is rebalanced.

An interconnection system including a first gating unit and a second gating unit is provided. The first gating unit includes two terminals, with one terminal connecting to a first CPU directly, where the two terminals are indirectly connected when the first gating unit is in a first state. The second gating unit includes two terminals, with one terminal connecting to a second CPU, where the two terminals are connected when the second gating unit is in the first state. Another terminal of the first gating unit is connected to another terminal of the second gating unit. If both the first gating unit and the second gating unit are in the first state, the first CPU is connected to the second CPU.