A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.

In an embodiment, an example computer-implemented method for configuring a hardware accelerator to perform a non-linear function involves: determining a plurality of intervals that partition an input domain of the non-linear function; determining a plurality of subinterval configurations corresponding to different numbers of subintervals for partitioning that interval; generating an error set comprising an error for using a polynomial function to approximate the non-linear function within one or more corresponding subintervals specified by the subinterval configuration; using the error set and resource constraints, selecting one of the subinterval configurations for each of the intervals to generate a configuration set that minimizes a worst-case error across the intervals; selecting one of the subinterval configurations for each of the intervals to generate an improved configuration set that minimizes a cumulative error across the intervals without exceeding the worst-case error; and configuring the hardware accelerator based on the improved configuration set.

An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

A data transformation apparatus selects items one by one and generates a first weight dataset and a second weight dataset on the basis of similarity between first records in a first dataset and second records in a second datasets. The first records and second records respectively include first item values and second item values that belong to the selected item. Based on the first weight dataset, the data transformation apparatus transforms the first dataset into a first similarity-determining dataset including third records. Each third record includes a numerical value that indicates a relationship between transformed item values belonging to different items. Further, based on the second weight dataset, the data transformation apparatus transforms the second dataset into a second similarity-determining dataset including fourth records. Each fourth record includes a numerical value that indicates a relationship between transformed item values belonging to different items.

An artificial intelligence (AI) system is disclosed. The AI system provides an energy efficient hyper parallel and pipelined temporal and spatial scalable secure AI hardware with minimized external memory access. One or more than one re-configurable AI compute engine blocks may be interconnected via one or more high speed interconnect busses to enable an AI processing chain and data exchange between themselves. A hardware sequencer is disclosed to enable an AI processing chain execution driven by dynamically composed AI processing chains.

A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

A method including receiving a first configuration of a device validated against a design constraint, is provided. A configuration includes stimuli controls and stimuli parameters used as inputs in a device model. The method includes determining a quality of the first configuration based on an estimation of an output parameter including a desired behavior of the device, simulating the device in the first configuration when the first configuration quality overcomes a threshold, and requesting a second configuration of the device when the quality of the first configuration is below the selected threshold. The method also includes obtaining a regression based on multiple, high quality configurations to determine, for the device, a distribution of output parameter values and comparing the distribution of output parameter values with a baseline of a random regression to adjust the machine learning engine according to a target range of output parameter values.